Simulation Results: flash_ctrl

 
17/03/2026 17:25:29 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.36 %
  • code
  • 94.27 %
  • assert
  • 95.90 %
  • func
  • 95.91 %
  • line
  • 96.02 %
  • branch
  • 97.08 %
  • cond
  • 93.85 %
  • toggle
  • 98.01 %
  • FSM
  • 86.39 %
Validation stages
V1
100.00%
V2
100.00%
V2S
97.73%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 29.490s 0.000us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 10.900s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 19.140s 0.000us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.490s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 27.490s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 19.500s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.930s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.490s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 19.500s 0.000us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 7.430s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.510s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 11.300s 0.000us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 33.050s 0.000us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1152.230s 0.000us 1 1 100.00
flash_ctrl_hw_rma_reset 594.440s 0.000us 1 1 100.00
flash_ctrl_lcmgr_intg 5.280s 0.000us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1625.420s 0.000us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 122.200s 0.000us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 99.950s 0.000us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1900.330s 0.000us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 38.540s 0.000us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 14.760s 0.000us 1 1 100.00
flash_ctrl_rw_evict_all_en 16.610s 0.000us 1 1 100.00
flash_ctrl_re_evict 17.490s 0.000us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 38.190s 0.000us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 38.190s 0.000us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 187.830s 0.000us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 11.940s 0.000us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 51.860s 0.000us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 543.770s 0.000us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 327.520s 0.000us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 927.910s 0.000us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.890s 0.000us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 107.880s 0.000us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.710s 0.000us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 7.220s 0.000us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 237.130s 0.000us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 93.400s 0.000us 1 1 100.00
flash_ctrl_otp_reset 50.240s 0.000us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1152.230s 0.000us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 115.330s 0.000us 1 1 100.00
flash_ctrl_intr_wr 64.180s 0.000us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 79.080s 0.000us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 166.440s 0.000us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 38.930s 0.000us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 35.900s 0.000us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 9.840s 0.000us 1 1 100.00
flash_ctrl_ro_derr 99.740s 0.000us 1 1 100.00
flash_ctrl_rw_derr 147.000s 0.000us 1 1 100.00
flash_ctrl_derr_detect 104.530s 0.000us 1 1 100.00
flash_ctrl_integrity 387.650s 0.000us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 9.120s 0.000us 1 1 100.00
flash_ctrl_ro_serr 85.350s 0.000us 1 1 100.00
flash_ctrl_rw_serr 125.680s 0.000us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 70.340s 0.000us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 69.280s 0.000us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 112.070s 0.000us 1 1 100.00
flash_ctrl_write_word_sweep 6.740s 0.000us 1 1 100.00
flash_ctrl_read_word_sweep 7.640s 0.000us 1 1 100.00
flash_ctrl_ro 74.830s 0.000us 1 1 100.00
flash_ctrl_rw 389.270s 0.000us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 25.530s 0.000us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 920.830s 0.000us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 63.080s 0.000us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.590s 0.000us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 8.480s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.960s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.960s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 19.140s 0.000us 1 1 100.00
flash_ctrl_csr_rw 7.490s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 19.500s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.680s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 19.140s 0.000us 1 1 100.00
flash_ctrl_csr_rw 7.490s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 19.500s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 8.680s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 23.900s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 23.900s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 23.900s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 23.900s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 34.560s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 180.430s 0.000us 1 1 100.00
flash_ctrl_sec_cm 1487.640s 0.000us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 180.430s 0.000us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 180.430s 0.000us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.420s 0.000us 1 1 100.00
flash_ctrl_wr_intg 6.770s 0.000us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 29.490s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 50.240s 0.000us 1 1 100.00
flash_ctrl_disable 9.710s 0.000us 1 1 100.00
flash_ctrl_sec_info_access 29.290s 0.000us 1 1 100.00
flash_ctrl_connect 7.220s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 8.070s 0.000us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.490s 0.000us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 23.900s 0.000us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.490s 0.000us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 23.900s 0.000us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.490s 0.000us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 23.900s 0.000us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.710s 0.000us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.420s 0.000us 1 1 100.00
flash_ctrl_access_after_disable 6.020s 0.000us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 12.860s 0.000us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.710s 0.000us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 11.940s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 389.270s 0.000us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 125.680s 0.000us 1 1 100.00
flash_ctrl_rw_derr 147.000s 0.000us 1 1 100.00
flash_ctrl_integrity 387.650s 0.000us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1152.230s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1487.640s 0.000us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1487.640s 0.000us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1487.640s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1487.640s 0.000us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.650s 0.000us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 5.390s 0.000us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 7.060s 0.000us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1487.640s 0.000us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1487.640s 0.000us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1487.640s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.250s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 13.800s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
flash_ctrl_phy_host_grant_err 65854393589036803257492625490888951646475362232656994995421057813513030820942 125
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
UVM_ERROR @ 81396.8 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 81396.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---