Simulation Results: i2c

 
17/03/2026 17:25:29 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.50 %
  • code
  • 81.48 %
  • assert
  • 96.19 %
  • func
  • 81.82 %
  • line
  • 96.41 %
  • branch
  • 92.33 %
  • cond
  • 84.97 %
  • toggle
  • 89.66 %
  • FSM
  • 44.05 %
Validation stages
V1
100.00%
V2
89.80%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 44.630s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 11.480s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.670s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.700s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.310s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 0.980s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.780s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.700s 0.000us 1 1 100.00
i2c_csr_aliasing 0.980s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.750s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 0.870s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 178.010s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.700s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 45.800s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 100.370s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.950s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 9.950s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 2.930s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 48.540s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 19.990s 0.000us 1 1 100.00
i2c_host_mode_toggle 0 1 0.00
i2c_host_mode_toggle 0.660s 0.000us 0 1 0.00
target_glitch 0 1 0.00
i2c_target_glitch 1.920s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 133.080s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 3.340s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 25.440s 0.000us 1 1 100.00
i2c_target_intr_smoke 3.030s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.030s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 1.220s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 29.020s 0.000us 1 1 100.00
i2c_target_stress_rd 25.440s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 2.430s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.350s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 17.050s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.440s 0.000us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 3.070s 0.000us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.800s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.940s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 178.010s 0.000us 1 1 100.00
i2c_host_perf_precise 11.670s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 19.990s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 7.380s 0.000us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.960s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.770s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.030s 0.000us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 3.740s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.490s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.770s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.650s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.250s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.250s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.670s 0.000us 1 1 100.00
i2c_csr_rw 0.700s 0.000us 1 1 100.00
i2c_csr_aliasing 0.980s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.880s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.670s 0.000us 1 1 100.00
i2c_csr_rw 0.700s 0.000us 1 1 100.00
i2c_csr_aliasing 0.980s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.880s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 0.880s 0.000us 1 1 100.00
i2c_tl_intg_err 1.760s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.760s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 18.090s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 0.980s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 5.270s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 31833668854567302218389901461533899961350504875456189756119594713587982224517 94
UVM_ERROR @ 83608470 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 83608470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 92935299254309665850808026729449087822157936468274810081711238877237437647571 98
UVM_ERROR @ 93283417 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 93283417 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_mode_toggle 66443222990766964991631088540420821731959129133607043233040386419792764622420 81
UVM_ERROR @ 15549336 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 15549336 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 104505652875256354369368255957859287278925751059461471122676220079781522354169 84
UVM_ERROR @ 3211520791 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 3211520791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
i2c_target_unexp_stop 49790032012480409104985665932547831766218254859448343213388720245736717736316 79
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 184168008 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 184168008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 82870212204094920881920270672444472441737408157040105674570177586824497572467 79
UVM_FATAL @ 11753012588 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 11753012588 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 59658114264758763630208218489868081660877407811791841027571070511011943312584 89
UVM_ERROR @ 577875660 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 577875660 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 109616667992496282226263386840417442373137179416419266984924740656656008580327 84
UVM_ERROR @ 389310321 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 389310321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---