Simulation Results: kmac/unmasked

 
17/03/2026 17:25:29 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.26 %
  • code
  • 88.68 %
  • assert
  • 97.75 %
  • func
  • 93.36 %
  • line
  • 97.32 %
  • branch
  • 95.41 %
  • cond
  • 93.78 %
  • toggle
  • 99.87 %
  • FSM
  • 57.02 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 47.470s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.800s 0.000us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.920s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 6.680s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 6.450s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.280s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.920s 0.000us 1 1 100.00
kmac_csr_aliasing 6.450s 0.000us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.830s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.270s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 143.580s 0.000us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 467.860s 0.000us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1532.170s 0.000us 1 1 100.00
kmac_test_vectors_sha3_256 1091.930s 0.000us 1 1 100.00
kmac_test_vectors_sha3_384 811.280s 0.000us 1 1 100.00
kmac_test_vectors_sha3_512 13.830s 0.000us 1 1 100.00
kmac_test_vectors_shake_128 103.200s 0.000us 1 1 100.00
kmac_test_vectors_shake_256 1098.090s 0.000us 1 1 100.00
kmac_test_vectors_kmac 2.050s 0.000us 1 1 100.00
kmac_test_vectors_kmac_xof 1.850s 0.000us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 233.370s 0.000us 1 1 100.00
app 1 1 100.00
kmac_app 32.010s 0.000us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 130.570s 0.000us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 148.600s 0.000us 1 1 100.00
error 1 1 100.00
kmac_error 91.950s 0.000us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 7.590s 0.000us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 14.390s 0.000us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 2.200s 0.000us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 20.360s 0.000us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 38.080s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 8.040s 0.000us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 1365.790s 0.000us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.850s 0.000us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 1.060s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.750s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.750s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.800s 0.000us 1 1 100.00
kmac_csr_rw 0.920s 0.000us 1 1 100.00
kmac_csr_aliasing 6.450s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.790s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.800s 0.000us 1 1 100.00
kmac_csr_rw 0.920s 0.000us 1 1 100.00
kmac_csr_aliasing 6.450s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.790s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.820s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.820s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.820s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.820s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.980s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 63.870s 0.000us 1 1 100.00
kmac_tl_intg_err 3.150s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.150s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 8.040s 0.000us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 47.470s 0.000us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 233.370s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.820s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 63.870s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 63.870s 0.000us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 63.870s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 47.470s 0.000us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 8.040s 0.000us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 63.870s 0.000us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 256.350s 0.000us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 47.470s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 175.370s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=8)
kmac_sideload_invalid 15578146690616327199556873368386374595425598230608233469459184495053617534660 84
UVM_FATAL @ 10342764478 ps: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=0xa49b5000, Comparison=CompareOpEq, exp_data=0x1, call_count=8)
UVM_INFO @ 10342764478 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---