Simulation Results: otp_ctrl

 
17/03/2026 17:25:29 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.79 %
  • code
  • 77.19 %
  • assert
  • 91.94 %
  • func
  • 67.25 %
  • line
  • 88.53 %
  • branch
  • 81.94 %
  • cond
  • 89.25 %
  • toggle
  • 82.46 %
  • FSM
  • 43.75 %
Validation stages
V1
100.00%
V2
96.00%
V2S
55.36%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.950s 0.000us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.360s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.620s 0.000us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.420s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.450s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.100s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.790s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.420s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 3.100s 0.000us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.600s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.470s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 13.740s 0.000us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.930s 0.000us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 3.530s 0.000us 1 1 100.00
otp_ctrl_check_fail 1.980s 0.000us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 6.920s 0.000us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 38.520s 0.000us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 10.030s 0.000us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 13.690s 0.000us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 27.960s 0.000us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 6.170s 0.000us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 35.710s 0.000us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 14.620s 0.000us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.740s 0.000us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.450s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.150s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.150s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.620s 0.000us 1 1 100.00
otp_ctrl_csr_rw 1.420s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 3.100s 0.000us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.170s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.620s 0.000us 1 1 100.00
otp_ctrl_csr_rw 1.420s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 3.100s 0.000us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.170s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_tl_intg_err 7.620s 0.000us 1 1 100.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.620s 0.000us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.360s 0.000us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.360s 0.000us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
otp_ctrl_macro_errs 6.170s 0.000us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
otp_ctrl_macro_errs 6.170s 0.000us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.080s 0.000us 1 1 100.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.930s 0.000us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 1.980s 0.000us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 38.520s 0.000us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 38.520s 0.000us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 38.520s 0.000us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 38.520s 0.000us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 38.520s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.360s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 38.520s 0.000us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.360s 0.000us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 14.630s 0.000us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 6.920s 0.000us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.360s 0.000us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.360s 0.000us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 6.170s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 17.620s 0.000us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.350s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 55281279712187410395823176785708971674799386309687659938774356312540446839435 445
UVM_ERROR @ 93076463 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (96879613 [0x5c643fd] vs 96880637 [0x5c647fd]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0
UVM_INFO @ 93076463 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 19883710271542635559072333681947999091824618024796972966556864772907244474130 92
UVM_ERROR @ 54519881 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 54519881 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 95288901920034882153075149083582672991685925636622564810217210378817912361949 269
UVM_ERROR @ 12196295281 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 12196295281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---