Simulation Results: pattgen

 
17/03/2026 17:25:29 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.08 %
  • code
  • 98.87 %
  • assert
  • 96.95 %
  • func
  • 89.42 %
  • block
  • 100.00 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • toggle
  • 96.61 %
Validation stages
V1
100.00%
V2
93.75%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 0.000us 1 1 100.00
pattgen_csr_aliasing 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 230.000s 0.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 26.000s 0.000us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 0.000us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 1.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 2.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 0.000us 1 1 100.00
pattgen_csr_rw 1.000s 0.000us 1 1 100.00
pattgen_csr_aliasing 2.000s 0.000us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 0.000us 1 1 100.00
pattgen_csr_rw 1.000s 0.000us 1 1 100.00
pattgen_csr_aliasing 2.000s 0.000us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 0.000us 1 1 100.00
pattgen_tl_intg_err 2.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 18.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
pattgen_perf 66500938994832381179248758380859396777640489522185232420319226157113644311045 99
UVM_FATAL @ 600000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 600000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 600000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
pattgen_stress_all_with_rand_reset 46463661282437183568718241819177657546781498821677572805774297975103590085560 115
UVM_ERROR @ 455149873 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_ERROR @ 455149900 ps: (cip_base_vseq.sv:1150) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 455149900 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
Issuing reset for run 1/5
UVM_INFO @ 455200405 ps: (cip_base_vseq.sv:1174) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]