Simulation Results: sysrst_ctrl

 
17/03/2026 17:25:29 DVSim: v1.16.0 sha: bb824c6 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.36 %
  • code
  • 90.36 %
  • assert
  • 89.75 %
  • func
  • 57.96 %
  • line
  • 95.72 %
  • branch
  • 96.48 %
  • cond
  • 92.52 %
  • toggle
  • 99.77 %
  • FSM
  • 67.31 %
Validation stages
V1
100.00%
V2
95.65%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 1.080s 0.000us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 5.220s 0.000us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.380s 0.000us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.180s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 1.570s 0.000us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 4.640s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 26.710s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 4.270s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.420s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 4.640s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.270s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 62.330s 0.000us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 3.910s 0.000us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 2.340s 0.000us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.150s 0.000us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 2.040s 0.000us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 6.520s 0.000us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 6.960s 0.000us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 6.300s 0.000us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 7.970s 0.000us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 19.190s 0.000us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 12.700s 0.000us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.980s 0.000us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 1.530s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.050s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.050s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.570s 0.000us 1 1 100.00
sysrst_ctrl_csr_rw 4.640s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.270s 0.000us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.430s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 1.570s 0.000us 1 1 100.00
sysrst_ctrl_csr_rw 4.640s 0.000us 1 1 100.00
sysrst_ctrl_csr_aliasing 4.270s 0.000us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 10.430s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_tl_intg_err 41.370s 0.000us 1 1 100.00
sysrst_ctrl_sec_cm 24.390s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 41.370s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 8.980s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
sysrst_ctrl_ultra_low_pwr 67242461875295596115634910578984607439953384228618580992586527252824498357391 650
UVM_ERROR @ 8094417300 ps: (cip_base_scoreboard.sv:255) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault has unexpected timeout error
UVM_ERROR @ 8094437918 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 8094437918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---