Simulation Results: adc_ctrl

 
19/03/2026 20:49:13 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.36 %
  • code
  • 96.93 %
  • assert
  • 95.95 %
  • func
  • 18.19 %
  • line
  • 99.05 %
  • branch
  • 97.77 %
  • cond
  • 93.26 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 1.410s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.560s 0.000us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.320s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 39.940s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.400s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.830s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.320s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 2.400s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 145.220s 0.000us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 518.610s 0.000us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 800.730s 0.000us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 258.940s 0.000us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 451.940s 0.000us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 150.900s 0.000us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 166.440s 0.000us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 41.540s 0.000us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 4.770s 0.000us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 14.120s 0.000us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 47.070s 0.000us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 495.210s 0.000us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.060s 0.000us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.910s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.490s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.490s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.560s 0.000us 1 1 100.00
adc_ctrl_csr_rw 1.320s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 2.400s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 8.700s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.560s 0.000us 1 1 100.00
adc_ctrl_csr_rw 1.320s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 2.400s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 8.700s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 1.750s 0.000us 1 1 100.00
adc_ctrl_sec_cm 6.660s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 1.750s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 6.120s 0.000us 1 1 100.00