Simulation Results: alert_handler

 
19/03/2026 20:49:13 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.62 %
  • code
  • 93.19 %
  • assert
  • 91.07 %
  • func
  • 78.61 %
  • line
  • 99.75 %
  • branch
  • 99.82 %
  • cond
  • 93.82 %
  • toggle
  • 93.54 %
  • FSM
  • 79.03 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 3.330s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 2.850s 0.000us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.340s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 62.130s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 110.060s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 7.300s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.340s 0.000us 1 1 100.00
alert_handler_csr_aliasing 110.060s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 35.590s 0.000us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 12.630s 0.000us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 403.490s 0.000us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 9.440s 0.000us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 3.330s 0.000us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 37.050s 0.000us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 17.690s 0.000us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 188.310s 0.000us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 1632.580s 0.000us 1 1 100.00
alert_handler_lpg_stub_clk 1361.580s 0.000us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1430.230s 0.000us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 9.560s 0.000us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 1.960s 0.000us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.430s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 9.560s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 9.560s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 2.850s 0.000us 1 1 100.00
alert_handler_csr_rw 5.340s 0.000us 1 1 100.00
alert_handler_csr_aliasing 110.060s 0.000us 1 1 100.00
alert_handler_same_csr_outstanding 25.030s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 2.850s 0.000us 1 1 100.00
alert_handler_csr_rw 5.340s 0.000us 1 1 100.00
alert_handler_csr_aliasing 110.060s 0.000us 1 1 100.00
alert_handler_same_csr_outstanding 25.030s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 85.740s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 85.740s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 85.740s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 85.740s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 593.860s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 8.900s 0.000us 1 1 100.00
alert_handler_tl_intg_err 30.690s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 30.690s 0.000us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 85.740s 0.000us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 3.330s 0.000us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 3.330s 0.000us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 3.330s 0.000us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 3.330s 0.000us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 9.440s 0.000us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1632.580s 0.000us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 9.440s 0.000us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 403.490s 0.000us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 403.490s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.900s 0.000us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.900s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.900s 0.000us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.900s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 8.900s 0.000us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.900s 0.000us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.900s 0.000us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.900s 0.000us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 8.900s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 142.030s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1149) [alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
alert_handler_stress_all_with_rand_reset 22722362449097072065962078006672786498523240072629986944049104577340096232862 161
UVM_ERROR @ 3294671171 ps: (cip_base_vseq.sv:1149) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 3294671171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---