Simulation Results: chip

 
19/03/2026 20:49:13 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 75.71 %
  • code
  • 85.12 %
  • assert
  • 97.37 %
  • func
  • 44.63 %
  • line
  • 94.36 %
  • branch
  • 93.66 %
  • cond
  • 89.10 %
  • toggle
  • 91.35 %
  • FSM
  • 57.14 %
Validation stages
V1
95.65%
V2
85.29%
V2S
100.00%
V3
60.00%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 157.470s 0.000us 1 1 100.00
chip_sw_example_rom 64.050s 0.000us 1 1 100.00
chip_sw_example_manufacturer 103.760s 0.000us 1 1 100.00
chip_sw_example_concurrency 160.020s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 271.920s 0.000us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 200.110s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 2286.740s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 5069.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 307.860s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 5069.000s 0.000us 1 1 100.00
chip_csr_rw 200.110s 0.000us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.200s 0.000us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 294.560s 0.000us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 294.560s 0.000us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 294.560s 0.000us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 391.620s 0.000us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 391.620s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx1 373.630s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx2 375.890s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx3 356.650s 0.000us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 897.410s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1794.890s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 293.940s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 211.500s 0.000us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 211.500s 0.000us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 230.730s 0.000us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 306.570s 0.000us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 170.670s 0.000us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 629.470s 0.000us 1 1 100.00
chip_tap_straps_testunlock0 336.000s 0.000us 1 1 100.00
chip_tap_straps_rma 564.780s 0.000us 1 1 100.00
chip_tap_straps_prod 782.660s 0.000us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 161.410s 0.000us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 838.240s 0.000us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 353.420s 0.000us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 353.420s 0.000us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 673.930s 0.000us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1164.790s 0.000us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.300s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 545.720s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3551.300s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 145.640s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 669.290s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 155.750s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 574.050s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 179.610s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 396.000s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 143.210s 0.000us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 231.470s 0.000us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 583.920s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 268.340s 0.000us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 128.220s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 268.340s 0.000us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 190.130s 0.000us 1 1 100.00
chip_sw_aes_smoketest 130.640s 0.000us 1 1 100.00
chip_sw_aon_timer_smoketest 189.150s 0.000us 1 1 100.00
chip_sw_clkmgr_smoketest 171.080s 0.000us 1 1 100.00
chip_sw_csrng_smoketest 115.610s 0.000us 1 1 100.00
chip_sw_entropy_src_smoketest 895.700s 0.000us 1 1 100.00
chip_sw_gpio_smoketest 151.370s 0.000us 1 1 100.00
chip_sw_hmac_smoketest 178.690s 0.000us 1 1 100.00
chip_sw_kmac_smoketest 209.470s 0.000us 1 1 100.00
chip_sw_otbn_smoketest 1106.210s 0.000us 1 1 100.00
chip_sw_pwrmgr_smoketest 281.490s 0.000us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 251.730s 0.000us 1 1 100.00
chip_sw_rv_plic_smoketest 141.750s 0.000us 1 1 100.00
chip_sw_rv_timer_smoketest 184.000s 0.000us 1 1 100.00
chip_sw_rstmgr_smoketest 156.010s 0.000us 1 1 100.00
chip_sw_sram_ctrl_smoketest 119.290s 0.000us 1 1 100.00
chip_sw_uart_smoketest 165.050s 0.000us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 119.770s 0.000us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 325.650s 0.000us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7703.580s 0.000us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2565.920s 0.000us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 149.460s 0.000us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 185.730s 0.000us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 206.890s 0.000us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6844.080s 0.000us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7210.460s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 58.140s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 58.140s 0.000us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 5069.000s 0.000us 1 1 100.00
chip_same_csr_outstanding 3259.410s 0.000us 1 1 100.00
chip_csr_hw_reset 271.920s 0.000us 1 1 100.00
chip_csr_rw 200.110s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 5069.000s 0.000us 1 1 100.00
chip_same_csr_outstanding 3259.410s 0.000us 1 1 100.00
chip_csr_hw_reset 271.920s 0.000us 1 1 100.00
chip_csr_rw 200.110s 0.000us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 44.030s 0.000us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.260s 0.000us 1 1 100.00
xbar_smoke_large_delays 46.780s 0.000us 1 1 100.00
xbar_smoke_slow_rsp 51.220s 0.000us 1 1 100.00
xbar_random_zero_delays 30.360s 0.000us 1 1 100.00
xbar_random_large_delays 181.570s 0.000us 1 1 100.00
xbar_random_slow_rsp 113.960s 0.000us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 19.090s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 16.450s 0.000us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 18.440s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 16.450s 0.000us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 23.450s 0.000us 1 1 100.00
xbar_access_same_device_slow_rsp 616.060s 0.000us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 25.150s 0.000us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 170.920s 0.000us 1 1 100.00
xbar_stress_all_with_error 113.690s 0.000us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 224.990s 0.000us 1 1 100.00
xbar_stress_all_with_reset_error 450.000s 0.000us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2565.920s 0.000us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2360.800s 0.000us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2592.910s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2025.760s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2563.490s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2507.060s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2553.370s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2486.810s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 19.560s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 19.230s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 23.020s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 19.490s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 18.070s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 16.970s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 16.750s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 15.900s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 16.240s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 16.440s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 17.590s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 17.370s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 19.380s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 18.780s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.890s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.900s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 17.450s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 17.580s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16.450s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 15.950s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 15.730s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 23.820s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 18.770s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.540s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 16.630s 0.000us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 1980.750s 0.000us 1 1 100.00
rom_e2e_asm_init_dev 2547.770s 0.000us 1 1 100.00
rom_e2e_asm_init_prod 2525.510s 0.000us 1 1 100.00
rom_e2e_asm_init_prod_end 2566.700s 0.000us 1 1 100.00
rom_e2e_asm_init_rma 2389.430s 0.000us 1 1 100.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 4359.460s 0.000us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 4217.670s 0.000us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 4187.920s 0.000us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2590.300s 0.000us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2823.950s 0.000us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2823.950s 0.000us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 198.840s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 145.640s 0.000us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 137.300s 0.000us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 158.110s 0.000us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1358.700s 0.000us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 178.390s 0.000us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 341.740s 0.000us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 312.250s 0.000us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 497.270s 0.000us 1 1 100.00
chip_plic_all_irqs_10 242.700s 0.000us 1 1 100.00
chip_plic_all_irqs_20 368.940s 0.000us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 218.710s 0.000us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1030.590s 0.000us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 171.740s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 116.810s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1107.750s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1256.990s 0.000us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 718.200s 0.000us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7185.670s 0.000us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 229.370s 0.000us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 281.490s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 229.370s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 432.470s 0.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 432.470s 0.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 334.330s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 292.880s 0.000us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 627.810s 0.000us 1 1 100.00
chip_sw_aes_idle 158.110s 0.000us 1 1 100.00
chip_sw_hmac_enc_idle 205.560s 0.000us 1 1 100.00
chip_sw_kmac_idle 151.640s 0.000us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 289.020s 0.000us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 366.980s 0.000us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 287.980s 0.000us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 262.700s 0.000us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 997.300s 0.000us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 394.870s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 378.990s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 365.610s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.560s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 421.770s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 331.230s 0.000us 1 1 100.00
chip_sw_ast_clk_outputs 673.930s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 500.010s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 365.610s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.560s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.300s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 545.720s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3551.300s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 145.640s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 669.290s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 155.750s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 574.050s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 179.610s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 396.000s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 143.210s 0.000us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 135.610s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 419.020s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 635.470s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3256.430s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 146.450s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 166.090s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1265.140s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 160.830s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 380.710s 0.000us 1 1 100.00
chip_sw_flash_init_reduced_freq 1099.260s 0.000us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2020.360s 0.000us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 673.930s 0.000us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 371.990s 0.000us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 208.780s 0.000us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 312.250s 0.000us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1107.750s 0.000us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 764.850s 0.000us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 169.430s 0.000us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 485.910s 0.000us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 170.250s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 4106.830s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 151.030s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 650.580s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 151.030s 0.000us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 764.850s 0.000us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 165.230s 0.000us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1147.260s 0.000us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 549.360s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 545.720s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 372.150s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 356.300s 0.000us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3567.480s 0.000us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1147.260s 0.000us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 240.580s 0.000us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1732.150s 0.000us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 176.270s 0.000us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3567.480s 0.000us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 176.270s 0.000us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 176.270s 0.000us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 176.270s 0.000us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 176.270s 0.000us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 312.250s 0.000us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 203.780s 0.000us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 516.170s 0.000us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 431.620s 0.000us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 431.620s 0.000us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 174.910s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 155.750s 0.000us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 205.560s 0.000us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1635.200s 0.000us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 709.300s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 455.840s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 471.830s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 428.340s 0.000us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 381.760s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1732.150s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 574.050s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1219.670s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1358.700s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2153.170s 0.000us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 140.370s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac 162.050s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 179.610s 0.000us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1732.150s 0.000us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 620.930s 0.000us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 127.080s 0.000us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1406.300s 0.000us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 151.640s 0.000us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 341.740s 0.000us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 629.470s 0.000us 1 1 100.00
chip_tap_straps_rma 564.780s 0.000us 1 1 100.00
chip_tap_straps_prod 782.660s 0.000us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 150.720s 0.000us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 620.930s 0.000us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 620.930s 0.000us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 620.930s 0.000us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1792.300s 0.000us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_prim_tl_access 203.780s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 257.980s 0.000us 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 176.270s 0.000us 0 1 0.00
chip_sw_flash_rma_unlocked 3567.480s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 176.360s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 464.750s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 559.690s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 573.370s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 620.930s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1732.150s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 345.670s 0.000us 1 1 100.00
chip_sw_sram_ctrl_execution_main 363.790s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 500.010s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 394.870s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 378.990s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 365.610s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 378.560s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 421.770s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 331.230s 0.000us 1 1 100.00
chip_tap_straps_dev 629.470s 0.000us 1 1 100.00
chip_tap_straps_rma 564.780s 0.000us 1 1 100.00
chip_tap_straps_prod 782.660s 0.000us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 192.390s 0.000us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 128.980s 0.000us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 99.750s 0.000us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 130.470s 0.000us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_rv_dm_lc_disabled 257.980s 0.000us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1710.640s 0.000us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 814.400s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prod 579.020s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prodend 713.740s 0.000us 1 1 100.00
chip_sw_lc_walkthrough_rma 342.980s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1710.640s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 50.050s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 55.660s 0.000us 1 1 100.00
rom_volatile_raw_unlock 65.930s 0.000us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3491.840s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3551.300s 0.000us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 627.810s 0.000us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 627.810s 0.000us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 627.810s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 307.240s 0.000us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 620.930s 0.000us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1147.260s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 307.240s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1732.150s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 330.850s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 138.680s 0.000us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1147.260s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 307.240s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1732.150s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 330.850s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 138.680s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 620.930s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 359.050s 0.000us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 150.720s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 203.780s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 176.360s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 464.750s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 559.690s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 573.370s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 620.930s 0.000us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 203.780s 0.000us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 771.020s 0.000us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 299.020s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1255.370s 0.000us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 286.900s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 323.400s 0.000us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 393.020s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 983.550s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 711.000s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 432.470s 0.000us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 783.030s 0.000us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 311.940s 0.000us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 299.020s 0.000us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 252.180s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2463.990s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 261.660s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 322.490s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 566.630s 0.000us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 606.830s 0.000us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1271.460s 0.000us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 2089.850s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 197.250s 0.000us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 312.250s 0.000us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 345.670s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 345.670s 0.000us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1271.460s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 566.630s 0.000us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 311.940s 0.000us 1 1 100.00
chip_sw_pwrmgr_smoketest 281.490s 0.000us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 242.950s 0.000us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 256.290s 0.000us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 281.880s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1030.590s 0.000us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 161.290s 0.000us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 312.250s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1256.990s 0.000us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 463.590s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 482.860s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 161.530s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 138.680s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 256.290s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 256.290s 0.000us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 584.180s 0.000us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 925.770s 0.000us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 242.950s 0.000us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 185.820s 0.000us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 333.530s 0.000us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 564.780s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 257.980s 0.000us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 497.270s 0.000us 1 1 100.00
chip_plic_all_irqs_10 242.700s 0.000us 1 1 100.00
chip_plic_all_irqs_20 368.940s 0.000us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 142.280s 0.000us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 209.820s 0.000us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2565.920s 0.000us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 527.800s 0.000us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 186.870s 0.000us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 227.560s 0.000us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 166.080s 0.000us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 330.850s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 396.000s 0.000us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 511.190s 0.000us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 490.410s 0.000us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 363.790s 0.000us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 312.250s 0.000us 1 1 100.00
chip_sw_data_integrity_escalation 353.420s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 606.830s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1247.290s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 190.640s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 233.990s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 286.990s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1247.290s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1247.290s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2327.690s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2327.690s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 356.030s 0.000us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2823.950s 0.000us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 120.900s 0.000us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 149.600s 0.000us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 336.870s 0.000us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 320.320s 0.000us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 968.700s 0.000us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4881.650s 0.000us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1847.960s 0.000us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 182.610s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 200.190s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 161.300s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9011.370s 0.000us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1062.450s 0.000us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 653.440s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 425.880s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 478.970s 0.000us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 88.700s 0.000us 0 1 0.00
rom_e2e_jtag_inject_dev 58.040s 0.000us 0 1 0.00
rom_e2e_jtag_inject_rma 63.190s 0.000us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 7.912s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 231.370s 0.000us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 281.730s 0.000us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 475.190s 0.000us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 796.080s 0.000us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 229.090s 0.000us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 570.210s 0.000us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 63.160s 0.000us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 189.990s 0.000us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 350.270s 0.000us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 260.300s 0.000us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1271.460s 0.000us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 653.440s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 425.880s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 478.970s 0.000us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 354.770s 0.000us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 312.250s 0.000us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5013.200s 0.000us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5013.200s 0.000us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 171.450s 0.000us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 391.620s 0.000us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2972.540s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 159.810s 0.000us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 378.960s 0.000us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.080s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 168.570s 0.000us 1 1 100.00
chip_sw_otp_ctrl_descrambling 208.050s 0.000us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 216.730s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.205s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 187.160s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 15122766271161403052079121598082104994978445125988067192901258406573095984435 217
UVM_ERROR @ 1939.288316 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@37947) { a_addr: 'h1047c a_data: 'h4b5c049d a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2d a_opcode: 'h4 a_user: 'h19907 d_param: 'h0 d_source: 'h2d d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 1939.288316 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 1912993523121555164866492028957764109399085247213475185944330743626102933838 242
UVM_ERROR @ 7159.388922 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@216933) { a_addr: 'h10468 a_data: 'h536b3ba7 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h3c a_opcode: 'h4 a_user: 'h1b163 d_param: 'h0 d_source: 'h3c d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 7159.388922 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 34146110632775985625574913197155545326500917251255863698667394613161931943051 333
UVM_ERROR @ 3720.950400 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@109337) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 3720.950400 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 103681916224102175742817265729055819138995118997574578604249340437422879357162 320
UVM_ERROR @ 2919.496612 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 2919.496612 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 73735943190737955880162297893352187408511176624512314514875173536776728143796 309
UVM_ERROR @ 3621.712416 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 3621.712416 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 62341623410500034900339502540144939764891019905835429655158734528188920623264 342
UVM_ERROR @ 7787.904788 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 7787.904788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 81920897655065349416508015018556581281417089564127126804032615045530986051985 316
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3254.564670 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3254.564670 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 8148433188069948022857045580783194878450633427769870653177699227561637383862 312
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2789.061616 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2789.061616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 54588263824339413633393858552962822370536047207482253897575495602609518668756 282
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 3389537472164901152940948434849530463759743135805878795370929821913987625235 369
UVM_ERROR @ 12588.395435 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 12588.395435 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 62330310774242526571815598713859824361781918361166135559254502443249606726723 369
UVM_ERROR @ 8571.438550 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 8571.438550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 100355463718805493703965098866403110184918327420844613149892837929894346338467 341
UVM_ERROR @ 7690.061985 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 7690.061985 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 69038587777850640828446816384590937034230332263272595358949282232993516533258 344
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 11818.805000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11818.805000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 29158206538284693250698485895066170768929096873476433918304773488191142085695 325
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7734.164000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7734.164000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 90835237373113783884698764423026180407690395597599110298072572644353300814271 319
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 8154.655000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 8154.655000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 40476886938641810276559732351454277191180539598580169617832715700631409051390 332
UVM_ERROR @ 34697.106949 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34697.106949 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:397)] CHECK-fail: Expect alert *!
chip_sw_alert_test 12173879931837937926304715233100881058549101355643488143956150784446826720944 307
UVM_ERROR @ 2876.402408 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:397)] CHECK-fail: Expect alert 53!
UVM_INFO @ 2876.402408 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 26397679990993411251792981031133302580777071461009666848833760825799305278931 308
UVM_ERROR @ 2575.860776 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2575.860776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 42126891356397245355101929810769402970714711891811872836641218749069851971092 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 37114762660993483984830291394845970737072855546765828022880148733717388649825 343
UVM_ERROR @ 3143.404470 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 3143.404470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 106532195020537849551706289222402591803324904645277104849327609541155585058662 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 100931076546620487090361304985922468818788789609010782424429981728321052161340 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 39891481333574360613743355059743013010797081538774190668848235895354651674699 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 62297155924693138094413016203932971835244954557121903238614061278660996474991 352
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 97858810333694837991951691292589806053235316190875124013288412990287490733998 352
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 38346626260118566744331236238907491245021252727792782771542734357160353655302 307
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 108075698680802263167440317806901330817790163910391998072449327454258325961732 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 104944844238353274148288690808823552631909665702489840102072894261604298249212 307
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 7404062392938644841816771719239461680127203275810623797313648910187303804317 312
UVM_ERROR @ 3072.365500 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3072.365500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 28103394205792506562105375090172631166374939043897422481483075307003181403168 318
UVM_ERROR @ 3658.480000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3658.480000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 33822631109558903973831141071048704895206654786517448300320549750302346615325 327
UVM_ERROR @ 11200.296686 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 11200.296686 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 12389178801543167603459538551109917208150852458381864267303821967196652220950 351
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 102843201755048796824291760455595555727721845832521354836037752404820702405925 348
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 96208691269838455413586121221167586039692557844087689637359928159757821921922 351
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 642666678397867738638457648729693332556601968786239352303476589651856952988 348
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 72177786705050215085652280440542462412634553466744032389382812894968556820825 351
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 100109178804813651123975052902319821201900956062944025919640002148263007026751 349
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 33893219493840210154017829315332445393106633706054031070140555888897667584172 346
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 72597012124960147270500205703261296221404049239362212963533292825698380421413 349
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 28531969281475346217375990749751553882690703940258257465562904308148318803504 347
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 7957970463729969551227313905126688760698006194629266076145766007028534332608 348
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 92678008011486254047239024841078719411964204594260432540995560576029290955169 359
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 102527262534463563543590262143964686890903638301983123862841252595709716119987 361
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 12925539423153647686286988635217059321549132861288037212474311205127877337955 359
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 2373051263512159378530950033550285931489903036777885440600276507141541647978 325
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 88935797556077989335926748032802335694798250676383205684132151555120435025107 323
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 62526351576538482343652974892250203810779754788998270653394681519835246373013 325
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 84102170442313028578331268567961870677454590879986162781129495424887688339739 357
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 104009907852505387415837883196727179406798855741948201637888946567554880652304 325
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 107402801912693576581524343906800853447977434731972379366917138471930465711868 361
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 112276010947283448600323581900017151727940449554466652729035220165848565624904 322
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 104537090166501205918202056237998421665708206358791541857234060797556402240131 324
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 111060545758172956630252315206283188284156803812851798200799669212236656405722 323
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 20656746693215162566160356166213422576484260869240589567249829885515455655103 322
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 2420341336475577246252677288868236238384896897399374344991637014322665203856 322
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 63591936327186765346078480109466873722662362569393263861402355171834912583440 324
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
rom_e2e_jtag_debug_test_unlocked0 114532722871015184116465247198045067100108116017596900688211290467610705706018 330
UVM_FATAL @ 14469.978710 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 14469.978710 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 681048583997986159848045178317523804653736562461210255164054611715959143912 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 5524.199510 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5524.199510 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---