Simulation Results: lc_ctrl/volatile_unlock_enabled

 
19/03/2026 20:49:13 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.64 %
  • code
  • 83.32 %
  • assert
  • 94.13 %
  • func
  • 91.46 %
  • line
  • 97.02 %
  • branch
  • 93.47 %
  • cond
  • 79.42 %
  • toggle
  • 86.89 %
  • FSM
  • 59.81 %
Validation stages
V1
100.00%
V2
95.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.480s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.940s 0.000us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.360s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.030s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.570s 0.000us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 13.900s 0.000us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.860s 0.000us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.620s 0.000us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.600s 0.000us 1 1 100.00
lc_errors 0 1 0.00
lc_ctrl_errors 5.650s 0.000us 0 1 0.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.600s 0.000us 1 1 100.00
lc_ctrl_prog_failure 1.620s 0.000us 1 1 100.00
lc_ctrl_errors 5.650s 0.000us 0 1 0.00
lc_ctrl_security_escalation 7.200s 0.000us 1 1 100.00
lc_ctrl_jtag_state_failure 13.540s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.620s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 38.220s 0.000us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.250s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.330s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.620s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 38.220s 0.000us 1 1 100.00
lc_ctrl_jtag_access 5.470s 0.000us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 15.430s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.900s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.610s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.710s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.580s 0.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.080s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.440s 0.000us 1 1 100.00
lc_ctrl_jtag_alert_test 1.580s 0.000us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.890s 0.000us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.010s 0.000us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 11.170s 0.000us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.260s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.100s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.100s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.940s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.420s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.940s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.730s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.030s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.420s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.520s 0.000us 1 1 100.00
lc_ctrl_tl_intg_err 1.960s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.960s 0.000us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 13.900s 0.000us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.600s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.520s 0.000us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.600s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.520s 0.000us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.600s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.520s 0.000us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.600s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.520s 0.000us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.600s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.520s 0.000us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.600s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.520s 0.000us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.600s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.520s 0.000us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.600s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.520s 0.000us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.200s 0.000us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.570s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 5.330s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.700s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 8.700s 0.000us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.220s 0.000us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.120s 0.000us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.120s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 52.340s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_errors 39898576472818412461407353890575586423810623959678657701422223263490001198836 3342
UVM_ERROR @ 612730258 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 612730258 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 109764404922809580270548052913360383502511984267194515141757819838538777738282 10181
UVM_ERROR @ 20139599791 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 20139599791 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---