Simulation Results: otp_ctrl

 
19/03/2026 20:49:13 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.26 %
  • code
  • 76.16 %
  • assert
  • 92.13 %
  • func
  • 69.50 %
  • line
  • 88.53 %
  • branch
  • 81.90 %
  • cond
  • 89.36 %
  • toggle
  • 76.57 %
  • FSM
  • 44.44 %
Validation stages
V1
100.00%
V2
92.00%
V2S
51.79%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.410s 0.000us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 3.520s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.490s 0.000us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.500s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.510s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.900s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.350s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.500s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 4.900s 0.000us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.110s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.470s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 19.670s 0.000us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.600s 0.000us 1 1 100.00
partition_check 2 2 100.00
otp_ctrl_background_chks 5.850s 0.000us 1 1 100.00
otp_ctrl_check_fail 7.870s 0.000us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.040s 0.000us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 12.900s 0.000us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 23.060s 0.000us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 5.820s 0.000us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 11.950s 0.000us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 2.550s 0.000us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 11.410s 0.000us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 47.900s 0.000us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.220s 0.000us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.100s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 5.300s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 5.300s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.490s 0.000us 1 1 100.00
otp_ctrl_csr_rw 1.500s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 4.900s 0.000us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.460s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.490s 0.000us 1 1 100.00
otp_ctrl_csr_rw 1.500s 0.000us 1 1 100.00
otp_ctrl_csr_aliasing 4.900s 0.000us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.460s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
tl_intg_err 1 2 50.00
otp_ctrl_tl_intg_err 19.660s 0.000us 1 1 100.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 19.660s 0.000us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 3.520s 0.000us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 3.520s 0.000us 1 1 100.00
sec_cm_dai_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_kdi_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_lci_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_part_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_scrmbl_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_timer_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_dai_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_kdi_seed_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_kdi_entropy_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_lci_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_part_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_scrmbl_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_timer_integ_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_timer_cnsty_ctr_redun 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_timer_lfsr_redun 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_dai_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
otp_ctrl_macro_errs 2.550s 0.000us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
sec_cm_timer_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_dai_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
otp_ctrl_macro_errs 2.550s 0.000us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
sec_cm_timer_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.750s 0.000us 1 1 100.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.600s 0.000us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 7.870s 0.000us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 12.900s 0.000us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 12.900s 0.000us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 12.900s 0.000us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 12.900s 0.000us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 12.900s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 3.520s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 12.900s 0.000us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 3.520s 0.000us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 1 0.00
otp_ctrl_sec_cm 27.670s 0.000us 0 1 0.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.040s 0.000us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 3.520s 0.000us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 3.520s 0.000us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 2.550s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 11.850s 0.000us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.390s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:*
otp_ctrl_macro_errs 91830598824549605366464081434499861215789019149053874878186526532454018891239 583
UVM_ERROR @ 861439432 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_macro_error did not trigger max_delay:20
UVM_INFO @ 861439432 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 42365239859568971858552601089673117662089017778474464474184753586864081307722 92
UVM_ERROR @ 115005721 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1
UVM_INFO @ 115005721 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_stress_all 95037105923675706931462195349863600426094650231443696296695434454754498318927 28970
UVM_ERROR @ 11703057873 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger!
UVM_INFO @ 11703057873 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
otp_ctrl_sec_cm 49784928083405840420312370744547607275512987066082272606412943534543376147505 712
UVM_ERROR @ 9821304527 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
UVM_INFO @ 9821304527 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---