Simulation Results: pwrmgr

 
19/03/2026 20:49:13 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.17 %
  • code
  • 89.82 %
  • assert
  • 95.82 %
  • func
  • 96.87 %
  • line
  • 98.76 %
  • branch
  • 94.85 %
  • cond
  • 93.49 %
  • toggle
  • 90.02 %
  • FSM
  • 72.00 %
Validation stages
V1
100.00%
V2
95.45%
V2S
47.06%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.630s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.600s 0.000us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.660s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.380s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.830s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.760s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.660s 0.000us 1 1 100.00
pwrmgr_csr_aliasing 0.830s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.820s 0.000us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.820s 0.000us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.790s 0.000us 1 1 100.00
pwrmgr_lowpower_invalid 0.630s 0.000us 1 1 100.00
reset 1 2 50.00
pwrmgr_reset 0.800s 0.000us 1 1 100.00
pwrmgr_reset_invalid 0.850s 0.000us 0 1 0.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.800s 0.000us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.590s 0.000us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.790s 0.000us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.750s 0.000us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.790s 0.000us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.570s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.260s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.260s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.600s 0.000us 1 1 100.00
pwrmgr_csr_rw 0.660s 0.000us 1 1 100.00
pwrmgr_csr_aliasing 0.830s 0.000us 1 1 100.00
pwrmgr_same_csr_outstanding 0.710s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.600s 0.000us 1 1 100.00
pwrmgr_csr_rw 0.660s 0.000us 1 1 100.00
pwrmgr_csr_aliasing 0.830s 0.000us 1 1 100.00
pwrmgr_same_csr_outstanding 0.710s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.640s 0.000us 0 1 0.00
pwrmgr_tl_intg_err 0.580s 0.000us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.640s 0.000us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.640s 0.000us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.580s 0.000us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.470s 0.000us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.590s 0.000us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.710s 0.000us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 0 1 0.00
pwrmgr_esc_clk_rst_malfunc 0.560s 0.000us 0 1 0.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.640s 0.000us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.640s 0.000us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.640s 0.000us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.570s 0.000us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.580s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.780s 0.000us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.660s 0.000us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.660s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.710s 0.000us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 10.580s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
pwrmgr_esc_clk_rst_malfunc 100905912323343982603076960499369493715140757396040848926076222516361284489325 75
UVM_ERROR @ 7591989 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 7591989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_escalation_timeout 42683592584730209301643662539166105520012801740587427374046373188040505429497 75
UVM_ERROR @ 372460059 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
UVM_INFO @ 372460059 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:56) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitAckPwrUp
pwrmgr_reset_invalid 30363164288733423272657852156478537948668462553810556945795251779560500181426 268
UVM_FATAL @ 83943648 ps: (pwrmgr_reset_invalid_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitAckPwrUp
UVM_INFO @ 83943648 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_sec_cm 106809606152556019552654224207596372540128111593722768538021818058404858883272 84
UVM_ERROR @ 26177256 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 26177256 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_tl_intg_err 77211271121862985834575655461542074297583678821068534580089887886238681645825 78
UVM_ERROR @ 15349713 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 15349713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---