Simulation Results

Simulation Results: spi_device/1r1w

19/03/2026 20:49:13 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
83.82 %

code
92.33 %

assert
94.64 %

func
64.48 %

line
98.95 %

branch
98.13 %

cond
95.91 %

toggle
83.54 %

FSM
85.11 %

Validation stages

V1		100.00%
V2		96.15%
V2S		100.00%
unmapped		100.00%

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	15.680s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	0.970s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	1.540s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	16.710s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	5.940s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	2.030s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	1.540s	0.000us	1	1	100.00
	spi_device_csr_aliasing	5.940s	0.000us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	0.920s	0.000us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	1.410s	0.000us	1	1	100.00

50/52 passed

96.15 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	0.760s	0.000us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	0.850s	0.000us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	0.830s	0.000us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	2.090s	0.000us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	2.090s	0.000us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	0.940s	0.000us	1	1	100.00
	spi_device_tpm_sts_read	0.810s	0.000us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	16.740s	0.000us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	3.070s	0.000us	1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	37.250s	0.000us	1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	37.250s	0.000us	1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	4.630s	0.000us	1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	4.630s	0.000us	1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	4.630s	0.000us	1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	4.630s	0.000us	1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	4.630s	0.000us	1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	6.820s	0.000us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	5.930s	0.000us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	5.930s	0.000us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	5.930s	0.000us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	2.350s	0.000us	1	1	100.00
	spi_device_read_buffer_direct	2.980s	0.000us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	5.930s	0.000us	1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	218.630s	0.000us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	1.850s	0.000us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	1.850s	0.000us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	15.680s	0.000us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	29.330s	0.000us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	1.190s	0.000us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	0.730s	0.000us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	0.760s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	4.310s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	4.310s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	0.970s	0.000us	1	1	100.00
	spi_device_csr_rw	1.540s	0.000us	1	1	100.00
	spi_device_csr_aliasing	5.940s	0.000us	1	1	100.00
	spi_device_same_csr_outstanding	1.680s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	0.970s	0.000us	1	1	100.00
	spi_device_csr_rw	1.540s	0.000us	1	1	100.00
	spi_device_csr_aliasing	5.940s	0.000us	1	1	100.00
	spi_device_same_csr_outstanding	1.680s	0.000us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	6.460s	0.000us	1	1	100.00
	spi_device_sec_cm	1.060s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	6.460s	0.000us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	310.010s	0.000us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
	spi_device_mem_parity	46163141245394407501353799029621864943606826699435770148744740435824850939082	76	UVM_ERROR @ 792525 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[69]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM_ERROR @ 792525 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) UVM_ERROR @ 792525 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[965]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	78376323430133943196991832130886257114962307711264778341434958527937220817320	76	UVM_ERROR @ 1016214 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5ed44f [10111101101010001001111] vs 0x0 [0]) UVM_ERROR @ 1101214 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa384eb [101000111000010011101011] vs 0x0 [0]) UVM_ERROR @ 1145214 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6ffccc [11011111111110011001100] vs 0x0 [0]) UVM_ERROR @ 1231214 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb4256 [10110100001001010110] vs 0x0 [0]) UVM_ERROR @ 1249214 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7034be [11100000011010010111110] vs 0x0 [0])