Simulation Results: uart

 
19/03/2026 20:49:13 DVSim: v1.16.0 sha: 1b83ebf json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.95 %
  • code
  • 95.47 %
  • assert
  • 97.12 %
  • func
  • 56.25 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 94.17 %
  • toggle
  • 91.32 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.560s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.730s 0.000us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.720s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.610s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.740s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.150s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.720s 0.000us 1 1 100.00
uart_csr_aliasing 0.740s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 49.570s 0.000us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.560s 0.000us 1 1 100.00
uart_tx_rx 49.570s 0.000us 1 1 100.00
parity_error 2 2 100.00
uart_intr 37.780s 0.000us 1 1 100.00
uart_rx_parity_err 31.880s 0.000us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 49.570s 0.000us 1 1 100.00
uart_intr 37.780s 0.000us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 89.810s 0.000us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 9.140s 0.000us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 81.640s 0.000us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 37.780s 0.000us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 37.780s 0.000us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 37.780s 0.000us 1 1 100.00
perf 1 1 100.00
uart_perf 674.570s 0.000us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.850s 0.000us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.850s 0.000us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 132.630s 0.000us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 50.190s 0.000us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 33.760s 0.000us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 19.210s 0.000us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 111.770s 0.000us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 50.360s 0.000us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.790s 0.000us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.630s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.590s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.590s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.730s 0.000us 1 1 100.00
uart_csr_rw 0.720s 0.000us 1 1 100.00
uart_csr_aliasing 0.740s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.850s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.730s 0.000us 1 1 100.00
uart_csr_rw 0.720s 0.000us 1 1 100.00
uart_csr_aliasing 0.740s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.850s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.220s 0.000us 1 1 100.00
uart_tl_intg_err 1.180s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.180s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 48.690s 0.000us 1 1 100.00