Simulation Results: alert_handler

 
23/03/2026 17:39:54 DVSim: v1.16.0 sha: 31add12 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.45 %
  • code
  • 92.78 %
  • assert
  • 98.23 %
  • func
  • 80.34 %
  • line
  • 99.70 %
  • branch
  • 99.79 %
  • cond
  • 94.64 %
  • toggle
  • 93.95 %
  • FSM
  • 75.81 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 17.510s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.570s 0.000us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 8.300s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 138.210s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 69.270s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 7.900s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 8.300s 0.000us 1 1 100.00
alert_handler_csr_aliasing 69.270s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 36.750s 0.000us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 4.550s 0.000us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 475.320s 0.000us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 29.150s 0.000us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 17.510s 0.000us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 8.830s 0.000us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 20.630s 0.000us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 94.270s 0.000us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1458.920s 0.000us 1 1 100.00
alert_handler_lpg_stub_clk 435.630s 0.000us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 806.790s 0.000us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 5.090s 0.000us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.480s 0.000us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.430s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 16.760s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 16.760s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.570s 0.000us 1 1 100.00
alert_handler_csr_rw 8.300s 0.000us 1 1 100.00
alert_handler_csr_aliasing 69.270s 0.000us 1 1 100.00
alert_handler_same_csr_outstanding 16.310s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.570s 0.000us 1 1 100.00
alert_handler_csr_rw 8.300s 0.000us 1 1 100.00
alert_handler_csr_aliasing 69.270s 0.000us 1 1 100.00
alert_handler_same_csr_outstanding 16.310s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 162.540s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 162.540s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 162.540s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 162.540s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 405.410s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 7.860s 0.000us 1 1 100.00
alert_handler_tl_intg_err 7.790s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 7.790s 0.000us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 162.540s 0.000us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 17.510s 0.000us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 17.510s 0.000us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 17.510s 0.000us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 17.510s 0.000us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 29.150s 0.000us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1458.920s 0.000us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 29.150s 0.000us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 475.320s 0.000us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 475.320s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 7.860s 0.000us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 7.860s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 7.860s 0.000us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 7.860s 0.000us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 7.860s 0.000us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.860s 0.000us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.860s 0.000us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.860s 0.000us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 7.860s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 97.650s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:483) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 88964607826060821697749405468736988355675748161303606487408163735902399314975 99
UVM_ERROR @ 13756667836 ps: (alert_handler_scoreboard.sv:483) [uvm_test_top.env.scoreboard] Check failed intr_state_val == item.d_data (0 [0x0] vs 4 [0x4]) reg name: intr_state
UVM_INFO @ 13756667836 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
alert_handler_stress_all_with_rand_reset 25625564043860647455070898114584849012023536144382965348473088923160620767900 130
UVM_ERROR @ 8625056210 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 8625056210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---