Simulation Results: hmac

 
23/03/2026 17:39:54 DVSim: v1.16.0 sha: 31add12 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.09 %
  • code
  • 98.01 %
  • assert
  • 96.70 %
  • func
  • 45.57 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.51 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.660s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.870s 0.000us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.880s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.080s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.530s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 558.320s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.880s 0.000us 1 1 100.00
hmac_csr_aliasing 3.530s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 55.410s 0.000us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 69.110s 0.000us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 162.660s 0.000us 1 1 100.00
hmac_test_sha384_vectors 19.080s 0.000us 1 1 100.00
hmac_test_sha512_vectors 18.890s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 6.100s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 6.290s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 9.510s 0.000us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 13.080s 0.000us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 471.180s 0.000us 1 1 100.00
error 1 1 100.00
hmac_error 71.210s 0.000us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 5.900s 0.000us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.660s 0.000us 1 1 100.00
hmac_long_msg 55.410s 0.000us 1 1 100.00
hmac_back_pressure 69.110s 0.000us 1 1 100.00
hmac_datapath_stress 471.180s 0.000us 1 1 100.00
hmac_burst_wr 13.080s 0.000us 1 1 100.00
hmac_stress_all 1621.810s 0.000us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.660s 0.000us 1 1 100.00
hmac_long_msg 55.410s 0.000us 1 1 100.00
hmac_back_pressure 69.110s 0.000us 1 1 100.00
hmac_datapath_stress 471.180s 0.000us 1 1 100.00
hmac_wipe_secret 5.900s 0.000us 1 1 100.00
hmac_test_sha256_vectors 162.660s 0.000us 1 1 100.00
hmac_test_sha384_vectors 19.080s 0.000us 1 1 100.00
hmac_test_sha512_vectors 18.890s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 6.100s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 6.290s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 9.510s 0.000us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.660s 0.000us 1 1 100.00
hmac_long_msg 55.410s 0.000us 1 1 100.00
hmac_back_pressure 69.110s 0.000us 1 1 100.00
hmac_datapath_stress 471.180s 0.000us 1 1 100.00
hmac_burst_wr 13.080s 0.000us 1 1 100.00
hmac_error 71.210s 0.000us 1 1 100.00
hmac_wipe_secret 5.900s 0.000us 1 1 100.00
hmac_test_sha256_vectors 162.660s 0.000us 1 1 100.00
hmac_test_sha384_vectors 19.080s 0.000us 1 1 100.00
hmac_test_sha512_vectors 18.890s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 6.100s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 6.290s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 9.510s 0.000us 1 1 100.00
hmac_stress_all 1621.810s 0.000us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1621.810s 0.000us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.690s 0.000us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.650s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.160s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.160s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.870s 0.000us 1 1 100.00
hmac_csr_rw 0.880s 0.000us 1 1 100.00
hmac_csr_aliasing 3.530s 0.000us 1 1 100.00
hmac_same_csr_outstanding 1.650s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.870s 0.000us 1 1 100.00
hmac_csr_rw 0.880s 0.000us 1 1 100.00
hmac_csr_aliasing 3.530s 0.000us 1 1 100.00
hmac_same_csr_outstanding 1.650s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.740s 0.000us 1 1 100.00
hmac_tl_intg_err 2.980s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.980s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.660s 0.000us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.130s 0.000us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 375.080s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.760s 0.000us 1 1 100.00