Simulation Results: i2c

 
23/03/2026 17:39:54 DVSim: v1.16.0 sha: 31add12 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.68 %
  • code
  • 81.57 %
  • assert
  • 96.19 %
  • func
  • 79.28 %
  • line
  • 96.38 %
  • branch
  • 92.33 %
  • cond
  • 85.04 %
  • toggle
  • 89.45 %
  • FSM
  • 44.64 %
Validation stages
V1
100.00%
V2
91.84%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 47.860s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 9.510s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.730s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 3.100s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 1.020s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 0.850s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
i2c_csr_aliasing 1.020s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.910s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 20.760s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 7.620s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.690s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 48.340s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 73.870s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 1.000s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 5.420s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 4.040s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 99.390s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 6.310s 0.000us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 1.670s 0.000us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 1.870s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 47.230s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 2.230s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 52.390s 0.000us 1 1 100.00
i2c_target_intr_smoke 3.110s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 0.660s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 0.870s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 12.070s 0.000us 1 1 100.00
i2c_target_stress_rd 52.390s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 6.450s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 4.560s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 11.310s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 2.650s 0.000us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 16.230s 0.000us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 1.040s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.840s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 7.620s 0.000us 1 1 100.00
i2c_host_perf_precise 4.400s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 6.310s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 1.540s 0.000us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 1.940s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.820s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.200s 0.000us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 4.810s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.670s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.570s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.650s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.840s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.840s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.730s 0.000us 1 1 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
i2c_csr_aliasing 1.020s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.950s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.730s 0.000us 1 1 100.00
i2c_csr_rw 0.710s 0.000us 1 1 100.00
i2c_csr_aliasing 1.020s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.950s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_sec_cm 0.830s 0.000us 1 1 100.00
i2c_tl_intg_err 1.210s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.210s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 14.910s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 1.380s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 7.590s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 44238268988296169513502911553887268486843508023394184300451147977526451920893 94
UVM_ERROR @ 8379305 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 8379305 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 34691198606859620913189060687528142396208679646441722982071740703077543963264 117
UVM_ERROR @ 1772228693 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 1772228693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 103113566017817366459736703429193306065341065021253279737419568998140092128452 84
UVM_ERROR @ 883689268 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 883689268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (i2c_base_vseq.sv:1474) [i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (* [*] vs * [*])
i2c_target_unexp_stop 21193957077163406505446647815664782176355927804346548744054881924112571999201 78
UVM_ERROR @ 1026842326 ps: (i2c_base_vseq.sv:1474) [uvm_test_top.env.virtual_sequencer.i2c_target_ack_stop_vseq] Check failed obs_intr_state[intr] == exp_val (0 [0x0] vs 1 [0x1])
UVM_INFO @ 1026842326 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 27270774104586124030261547550599271263604099216799882501587336461367496582019 79
UVM_FATAL @ 10013710311 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10013710311 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 49224685449008990054879792647760190911878863500437418619644820397655456647187 89
UVM_ERROR @ 744647793 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 744647793 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 80373596079083117894909311222249014641629394522203949189064640698965384918509 85
UVM_ERROR @ 1329288261 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1329288261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---