Simulation Results: lc_ctrl/volatile_unlock_enabled

 
23/03/2026 17:39:54 DVSim: v1.16.0 sha: 31add12 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.86 %
  • code
  • 84.67 %
  • assert
  • 94.13 %
  • func
  • 93.77 %
  • line
  • 97.24 %
  • branch
  • 94.07 %
  • cond
  • 80.04 %
  • toggle
  • 87.53 %
  • FSM
  • 64.49 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.300s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.340s 0.000us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.190s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.110s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.220s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.190s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.260s 0.000us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.360s 0.000us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.930s 0.000us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.170s 0.000us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.320s 0.000us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 9.400s 0.000us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.320s 0.000us 1 1 100.00
lc_ctrl_prog_failure 2.170s 0.000us 1 1 100.00
lc_ctrl_errors 9.400s 0.000us 1 1 100.00
lc_ctrl_security_escalation 6.710s 0.000us 1 1 100.00
lc_ctrl_jtag_state_failure 16.570s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.480s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 19.090s 0.000us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 1.470s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.470s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.100s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 9.200s 0.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.050s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.490s 0.000us 1 1 100.00
lc_ctrl_jtag_alert_test 1.020s 0.000us 1 1 100.00
lc_ctrl_jtag_smoke 5.940s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.560s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.480s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 19.090s 0.000us 1 1 100.00
lc_ctrl_jtag_access 8.260s 0.000us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 23.260s 0.000us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 7.880s 0.000us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.770s 0.000us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 34.610s 0.000us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.880s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.340s 0.000us 1 1 100.00
lc_ctrl_csr_rw 1.190s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.340s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.340s 0.000us 1 1 100.00
lc_ctrl_csr_rw 1.190s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.010s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.340s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.760s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.890s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.760s 0.000us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.360s 0.000us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.320s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.890s 0.000us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.320s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.890s 0.000us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.320s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.890s 0.000us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.320s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.890s 0.000us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.320s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.890s 0.000us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.320s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.890s 0.000us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.320s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.890s 0.000us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.320s 0.000us 1 1 100.00
lc_ctrl_sec_cm 5.890s 0.000us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.710s 0.000us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.260s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.560s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.160s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.160s 0.000us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.330s 0.000us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.190s 0.000us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.190s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 46.680s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 47382846497267819681304424143854124280669749271461811875542056253703254111771 1840
UVM_ERROR @ 2252840273 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10001 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 2252840273 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---