Simulation Results

Simulation Results: spi_device/1r1w

23/03/2026 17:39:54 DVSim: v1.16.0 sha: 31add12 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.09 %

code
92.75 %

assert
94.64 %

func
70.88 %

line
99.02 %

branch
98.23 %

cond
95.75 %

toggle
83.54 %

FSM
87.23 %

Validation stages

V1		100.00%
V2		96.15%
V2S		100.00%
unmapped		100.00%

10/10 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	spi_device_flash_and_tpm	47.220s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	spi_device_csr_hw_reset	1.090s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	spi_device_csr_rw	1.560s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	spi_device_csr_bit_bash	14.520s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	spi_device_csr_aliasing	9.200s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	spi_device_csr_mem_rw_with_rand_reset	1.480s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	spi_device_csr_rw	1.560s	0.000us	1	1	100.00
	spi_device_csr_aliasing	9.200s	0.000us	1	1	100.00
mem_walk				1	1	100.00
	spi_device_mem_walk	0.750s	0.000us	1	1	100.00
mem_partial_access				1	1	100.00
	spi_device_mem_partial_access	1.720s	0.000us	1	1	100.00

50/52 passed

96.15 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
csb_read				1	1	100.00
	spi_device_csb_read	0.950s	0.000us	1	1	100.00
mem_parity				0	1	0.00
	spi_device_mem_parity	0.780s	0.000us	0	1	0.00
mem_cfg				0	1	0.00
	spi_device_ram_cfg	0.670s	0.000us	0	1	0.00
tpm_read				1	1	100.00
	spi_device_tpm_rw	1.550s	0.000us	1	1	100.00
tpm_write				1	1	100.00
	spi_device_tpm_rw	1.550s	0.000us	1	1	100.00
tpm_hw_reg				2	2	100.00
	spi_device_tpm_read_hw_reg	3.350s	0.000us	1	1	100.00
	spi_device_tpm_sts_read	0.730s	0.000us	1	1	100.00
tpm_fully_random_case				1	1	100.00
	spi_device_tpm_all	24.680s	0.000us	1	1	100.00
pass_cmd_filtering				2	2	100.00
	spi_device_pass_cmd_filtering	1.880s	0.000us	1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
pass_addr_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	21.470s	0.000us	1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
pass_payload_translation				2	2	100.00
	spi_device_pass_addr_payload_swap	21.470s	0.000us	1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
cmd_info_slots				1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
cmd_read_status				2	2	100.00
	spi_device_intercept	4.490s	0.000us	1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
cmd_read_jedec				2	2	100.00
	spi_device_intercept	4.490s	0.000us	1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
cmd_read_sfdp				2	2	100.00
	spi_device_intercept	4.490s	0.000us	1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
cmd_fast_read				2	2	100.00
	spi_device_intercept	4.490s	0.000us	1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
cmd_read_pipeline				2	2	100.00
	spi_device_intercept	4.490s	0.000us	1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
flash_cmd_upload				1	1	100.00
	spi_device_upload	2.060s	0.000us	1	1	100.00
mailbox_command				1	1	100.00
	spi_device_mailbox	11.820s	0.000us	1	1	100.00
mailbox_cross_outside_command				1	1	100.00
	spi_device_mailbox	11.820s	0.000us	1	1	100.00
mailbox_cross_inside_command				1	1	100.00
	spi_device_mailbox	11.820s	0.000us	1	1	100.00
cmd_read_buffer				2	2	100.00
	spi_device_flash_mode	6.240s	0.000us	1	1	100.00
	spi_device_read_buffer_direct	12.990s	0.000us	1	1	100.00
cmd_dummy_cycle				2	2	100.00
	spi_device_mailbox	11.820s	0.000us	1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
quad_spi				1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
dual_spi				1	1	100.00
	spi_device_flash_all	20.280s	0.000us	1	1	100.00
4b_3b_feature				1	1	100.00
	spi_device_cfg_cmd	3.290s	0.000us	1	1	100.00
write_enable_disable				1	1	100.00
	spi_device_cfg_cmd	3.290s	0.000us	1	1	100.00
TPM_with_flash_or_passthrough_mode				1	1	100.00
	spi_device_flash_and_tpm	47.220s	0.000us	1	1	100.00
tpm_and_flash_trans_with_min_inactive_time				1	1	100.00
	spi_device_flash_and_tpm_min_idle	52.350s	0.000us	1	1	100.00
stress_all				1	1	100.00
	spi_device_stress_all	179.720s	0.000us	1	1	100.00
alert_test				1	1	100.00
	spi_device_alert_test	0.770s	0.000us	1	1	100.00
intr_test				1	1	100.00
	spi_device_intr_test	0.730s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	spi_device_tl_errors	1.570s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	spi_device_tl_errors	1.570s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	spi_device_csr_hw_reset	1.090s	0.000us	1	1	100.00
	spi_device_csr_rw	1.560s	0.000us	1	1	100.00
	spi_device_csr_aliasing	9.200s	0.000us	1	1	100.00
	spi_device_same_csr_outstanding	3.050s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	spi_device_csr_hw_reset	1.090s	0.000us	1	1	100.00
	spi_device_csr_rw	1.560s	0.000us	1	1	100.00
	spi_device_csr_aliasing	9.200s	0.000us	1	1	100.00
	spi_device_same_csr_outstanding	3.050s	0.000us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	spi_device_tl_intg_err	12.970s	0.000us	1	1	100.00
	spi_device_sec_cm	1.100s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	spi_device_tl_intg_err	12.970s	0.000us	1	1	100.00

unmapped

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				1	1	100.00
	spi_device_flash_mode_ignore_cmds	29.360s	0.000us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
	spi_device_mem_parity	57851658506639897574997182532561645275609758079469134974679457593149408082514	76	UVM_ERROR @ 3380883 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[36]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name UVM_ERROR @ 3380883 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data)) UVM_ERROR @ 3380883 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[932]) Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [] vs [*])
	spi_device_ram_cfg	43647028109866042851929828919895452914299528696381829945551389139271045054139	76	UVM_ERROR @ 2035840 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x90ee94 [100100001110111010010100] vs 0x0 [0]) UVM_ERROR @ 2106840 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xa42f0 [10100100001011110000] vs 0x0 [0]) UVM_ERROR @ 2131840 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xcf40e2 [110011110100000011100010] vs 0x0 [0]) UVM_ERROR @ 2200840 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xb90b76 [101110010000101101110110] vs 0x0 [0]) UVM_ERROR @ 2291840 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x538ac0 [10100111000101011000000] vs 0x0 [0])