Simulation Results: uart

 
23/03/2026 17:39:54 DVSim: v1.16.0 sha: 31add12 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.48 %
  • code
  • 96.71 %
  • assert
  • 97.12 %
  • func
  • 59.62 %
  • line
  • 99.48 %
  • branch
  • 98.14 %
  • cond
  • 97.67 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.040s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.720s 0.000us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.780s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.350s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.950s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.940s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.780s 0.000us 1 1 100.00
uart_csr_aliasing 0.950s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 29.870s 0.000us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.040s 0.000us 1 1 100.00
uart_tx_rx 29.870s 0.000us 1 1 100.00
parity_error 2 2 100.00
uart_intr 34.410s 0.000us 1 1 100.00
uart_rx_parity_err 19.820s 0.000us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 29.870s 0.000us 1 1 100.00
uart_intr 34.410s 0.000us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 101.870s 0.000us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 24.360s 0.000us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 33.300s 0.000us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 34.410s 0.000us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 34.410s 0.000us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 34.410s 0.000us 1 1 100.00
perf 1 1 100.00
uart_perf 472.080s 0.000us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.930s 0.000us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.930s 0.000us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 15.430s 0.000us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 2.080s 0.000us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.180s 0.000us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 39.750s 0.000us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 289.820s 0.000us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 380.760s 0.000us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.710s 0.000us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.680s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.320s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.320s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.720s 0.000us 1 1 100.00
uart_csr_rw 0.780s 0.000us 1 1 100.00
uart_csr_aliasing 0.950s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.930s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.720s 0.000us 1 1 100.00
uart_csr_rw 0.780s 0.000us 1 1 100.00
uart_csr_aliasing 0.950s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.930s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.120s 0.000us 1 1 100.00
uart_tl_intg_err 1.280s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.280s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 38.170s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 85117315617009728987970691679660742518221794596501762895273570331098225075912 75
UVM_ERROR @ 10687041142 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 1, clk_pulses: 0
UVM_ERROR @ 10687051243 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 10687061344 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (154 [0x9a] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 10784808721 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR @ 10784808721 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0