Simulation Results: keymgr

 
24/03/2026 17:19:26 DVSim: v1.16.0 sha: 4125149 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.04 %
  • code
  • 91.42 %
  • assert
  • 97.49 %
  • func
  • 54.22 %
  • line
  • 98.70 %
  • branch
  • 97.40 %
  • cond
  • 92.34 %
  • toggle
  • 84.95 %
  • FSM
  • 83.72 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.700s 0.000us 1 1 100.00
random 1 1 100.00
keymgr_random 3.340s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.330s 0.000us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.930s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 9.810s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.680s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 0.990s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.930s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.680s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 13.660s 0.000us 1 1 100.00
sideload 3 4 75.00
keymgr_sideload 22.180s 0.000us 1 1 100.00
keymgr_sideload_kmac 0.970s 0.000us 0 1 0.00
keymgr_sideload_aes 4.220s 0.000us 1 1 100.00
keymgr_sideload_otbn 1.590s 0.000us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 3.850s 0.000us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.680s 0.000us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.900s 0.000us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.250s 0.000us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.730s 0.000us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.290s 0.000us 1 1 100.00
stress_all 0 1 0.00
keymgr_stress_all 14.110s 0.000us 0 1 0.00
intr_test 1 1 100.00
keymgr_intr_test 0.930s 0.000us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.870s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.980s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.980s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.330s 0.000us 1 1 100.00
keymgr_csr_rw 0.930s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.680s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 1.380s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.330s 0.000us 1 1 100.00
keymgr_csr_rw 0.930s 0.000us 1 1 100.00
keymgr_csr_aliasing 3.680s 0.000us 1 1 100.00
keymgr_same_csr_outstanding 1.380s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 2.590s 0.000us 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.820s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.820s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.820s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.820s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 3.570s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 2.590s 0.000us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.820s 0.000us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 13.660s 0.000us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 0.930s 0.000us 1 1 100.00
keymgr_random 3.340s 0.000us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 0.930s 0.000us 1 1 100.00
keymgr_random 3.340s 0.000us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 0.930s 0.000us 1 1 100.00
keymgr_random 3.340s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.680s 0.000us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.730s 0.000us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.730s 0.000us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.340s 0.000us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.250s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 1.820s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.680s 0.000us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.820s 0.000us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.820s 0.000us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.820s 0.000us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 4.630s 0.000us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 1.820s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 1.870s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert recov_operation_err did not trigger max_delay:*
keymgr_sideload_kmac 57969901556463640931521136431846503072508149523582530216336762181871658608228 112
UVM_ERROR @ 6041940 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert recov_operation_err did not trigger max_delay:4
UVM_INFO @ 6041940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) KMAC key at state StOwnerIntKey for Attestation Kmac
keymgr_stress_all 12949979425260611838654821676439569125802951971135869353466942967631880595167 2728
UVM_ERROR @ 390584276 ps: (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[1], act_key.key[0]} !== keys_a_array[state][cdi][dest] (10603543873287447454808090049844309805002441988402459892034996841489457757288149510492155909528261254607270219914610669072335868076380159789375326687666611 [0xca750af609e087684fe7727d596c4e2d9eea6c3e02432e5d8e2e73a9dfd2400c0df33cfdf1160ad310033edc93255da4ef773cc279a3750c626c1f30fe4921b3] vs 10603543873287447454808090049844309805002441988402459892034996841489457757288149510492155909528261254607270219914610669072335868076380159789375326687666611 [0xca750af609e087684fe7727d596c4e2d9eea6c3e02432e5d8e2e73a9dfd2400c0df33cfdf1160ad310033edc93255da4ef773cc279a3750c626c1f30fe4921b3]) KMAC key at state StOwnerIntKey for Attestation Kmac
UVM_INFO @ 390584276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 91700318513445921251324653381736773515267746294586246020531300747747666342615 158
UVM_ERROR @ 223600210 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 223600210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---