Simulation Results: kmac/unmasked

 
24/03/2026 17:19:26 DVSim: v1.16.0 sha: 4125149 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.72 %
  • code
  • 89.34 %
  • assert
  • 97.90 %
  • func
  • 90.91 %
  • line
  • 97.51 %
  • branch
  • 95.73 %
  • cond
  • 93.19 %
  • toggle
  • 99.96 %
  • FSM
  • 60.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 51.570s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.830s 0.000us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.980s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 6.910s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 5.810s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.630s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.980s 0.000us 1 1 100.00
kmac_csr_aliasing 5.810s 0.000us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.720s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.160s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1193.990s 0.000us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 610.150s 0.000us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 30.550s 0.000us 1 1 100.00
kmac_test_vectors_sha3_256 1076.780s 0.000us 1 1 100.00
kmac_test_vectors_sha3_384 872.240s 0.000us 1 1 100.00
kmac_test_vectors_sha3_512 745.310s 0.000us 1 1 100.00
kmac_test_vectors_shake_128 1875.820s 0.000us 1 1 100.00
kmac_test_vectors_shake_256 1453.790s 0.000us 1 1 100.00
kmac_test_vectors_kmac 2.030s 0.000us 1 1 100.00
kmac_test_vectors_kmac_xof 1.700s 0.000us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 183.890s 0.000us 1 1 100.00
app 1 1 100.00
kmac_app 77.310s 0.000us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 142.740s 0.000us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 63.880s 0.000us 1 1 100.00
error 1 1 100.00
kmac_error 110.580s 0.000us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 6.030s 0.000us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 1.660s 0.000us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 12.720s 0.000us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 24.590s 0.000us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 18.060s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.880s 0.000us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 79.790s 0.000us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.780s 0.000us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.820s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.780s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.780s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.830s 0.000us 1 1 100.00
kmac_csr_rw 0.980s 0.000us 1 1 100.00
kmac_csr_aliasing 5.810s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.830s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.830s 0.000us 1 1 100.00
kmac_csr_rw 0.980s 0.000us 1 1 100.00
kmac_csr_aliasing 5.810s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.830s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.220s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.220s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.220s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.220s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
kmac_shadow_reg_errors_with_csr_rw 1.150s 0.000us 0 1 0.00
tl_intg_err 2 2 100.00
kmac_sec_cm 18.800s 0.000us 1 1 100.00
kmac_tl_intg_err 3.050s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.050s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.880s 0.000us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 51.570s 0.000us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 183.890s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.220s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 18.800s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 18.800s 0.000us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 18.800s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 51.570s 0.000us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.880s 0.000us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 18.800s 0.000us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 250.780s 0.000us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 51.570s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 40.360s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: kmac_reg_block.prefix_* reset value: *
kmac_shadow_reg_errors_with_csr_rw 42570856702556936168720333378703878557932466018163262066410880934611503815125 129
UVM_ERROR @ 7141250 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (1324992302 [0x4ef9c72e] vs 3361169983 [0xc857623f]) Regname: kmac_reg_block.prefix_2 reset value: 0x0
UVM_INFO @ 7141250 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---