Simulation Results: lc_ctrl/volatile_unlock_disabled

 
24/03/2026 17:19:26 DVSim: v1.16.0 sha: 4125149 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.96 %
  • code
  • 83.23 %
  • assert
  • 94.13 %
  • func
  • 92.53 %
  • line
  • 97.17 %
  • branch
  • 93.82 %
  • cond
  • 79.03 %
  • toggle
  • 84.46 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.500s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.130s 0.000us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.060s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.360s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.080s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.060s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.250s 0.000us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.760s 0.000us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.940s 0.000us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.590s 0.000us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.500s 0.000us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.870s 0.000us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.500s 0.000us 1 1 100.00
lc_ctrl_prog_failure 1.590s 0.000us 1 1 100.00
lc_ctrl_errors 7.870s 0.000us 1 1 100.00
lc_ctrl_security_escalation 4.790s 0.000us 1 1 100.00
lc_ctrl_jtag_state_failure 24.480s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.830s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 29.670s 0.000us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 2.080s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_rw 2.650s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.610s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.890s 0.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.020s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.640s 0.000us 1 1 100.00
lc_ctrl_jtag_alert_test 1.760s 0.000us 1 1 100.00
lc_ctrl_jtag_smoke 3.400s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.590s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.830s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 29.670s 0.000us 1 1 100.00
lc_ctrl_jtag_access 9.710s 0.000us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.060s 0.000us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 20.160s 0.000us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.120s 0.000us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 38.250s 0.000us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.090s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.090s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.130s 0.000us 1 1 100.00
lc_ctrl_csr_rw 1.060s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.110s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.130s 0.000us 1 1 100.00
lc_ctrl_csr_rw 1.060s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.170s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.110s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.900s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.370s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.900s 0.000us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.760s 0.000us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.500s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.370s 0.000us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.500s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.370s 0.000us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.500s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.370s 0.000us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.500s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.370s 0.000us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.500s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.370s 0.000us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.500s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.370s 0.000us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.500s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.370s 0.000us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.500s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.370s 0.000us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.790s 0.000us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.250s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.590s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.610s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.610s 0.000us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.510s 0.000us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.560s 0.000us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 6.560s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 7.570s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all_with_rand_reset 64552828444792203282715652721277393189283207616468453593826296593640663875597 3905
UVM_ERROR @ 392466868 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 392466868 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---