Simulation Results: lc_ctrl/volatile_unlock_enabled

 
24/03/2026 17:19:26 DVSim: v1.16.0 sha: 4125149 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.89 %
  • code
  • 83.68 %
  • assert
  • 93.99 %
  • func
  • 91.99 %
  • line
  • 97.06 %
  • branch
  • 93.62 %
  • cond
  • 79.28 %
  • toggle
  • 86.77 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
95.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.060s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.820s 0.000us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.740s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.660s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.390s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.960s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.740s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.390s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.620s 0.000us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 3.920s 0.000us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.080s 0.000us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.630s 0.000us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.820s 0.000us 1 1 100.00
lc_errors 0 1 0.00
lc_ctrl_errors 5.040s 0.000us 0 1 0.00
security_escalation 6 7 85.71
lc_ctrl_state_failure 7.820s 0.000us 1 1 100.00
lc_ctrl_prog_failure 2.630s 0.000us 1 1 100.00
lc_ctrl_errors 5.040s 0.000us 0 1 0.00
lc_ctrl_security_escalation 4.800s 0.000us 1 1 100.00
lc_ctrl_jtag_state_failure 22.450s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.210s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 14.210s 0.000us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_csr_hw_reset 4.000s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.500s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.310s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 7.460s 0.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.050s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.060s 0.000us 1 1 100.00
lc_ctrl_jtag_alert_test 1.270s 0.000us 1 1 100.00
lc_ctrl_jtag_smoke 5.040s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 15.150s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 2.210s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 14.210s 0.000us 1 1 100.00
lc_ctrl_jtag_access 4.620s 0.000us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 7.370s 0.000us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.890s 0.000us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.740s 0.000us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 64.280s 0.000us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.960s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 3.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.740s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.390s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.990s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.820s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.740s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.390s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.990s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_tl_intg_err 1.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.240s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.290s 0.000us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 3.920s 0.000us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.820s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.240s 0.000us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.820s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.240s 0.000us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.820s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.240s 0.000us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.820s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.240s 0.000us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.820s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.240s 0.000us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.820s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.240s 0.000us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.820s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.240s 0.000us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.820s 0.000us 1 1 100.00
lc_ctrl_sec_cm 7.240s 0.000us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.800s 0.000us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.620s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 15.150s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.970s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.970s 0.000us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.010s 0.000us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.430s 0.000us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.430s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 41.030s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_errors 66904422167886117702685288377346778649693589065921370729537300027394824126995 3681
UVM_ERROR @ 310508026 ps: (lc_ctrl_errors_vseq.sv:768) [uvm_test_top.env.virtual_sequencer.lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (0 [0x0] vs 1 [0x1])
UVM_INFO @ 310508026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 11528018085464235037160313600726825040681038528346311895090953020182464593810 10923
UVM_ERROR @ 3122202322 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 3122202322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---