Simulation Results: pwm

 
24/03/2026 17:19:26 DVSim: v1.16.0 sha: 4125149 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 97.58 %
  • code
  • 96.07 %
  • assert
  • 98.00 %
  • func
  • 98.68 %
  • block
  • 99.02 %
  • line
  • 99.28 %
  • branch
  • 98.27 %
  • toggle
  • 90.65 %
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwm_smoke 14.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
pwm_csr_hw_reset 1.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
pwm_csr_rw 1.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
pwm_csr_bit_bash 4.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
pwm_csr_aliasing 2.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwm_csr_mem_rw_with_rand_reset 1.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwm_csr_rw 1.000s 0.000us 1 1 100.00
pwm_csr_aliasing 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dutycycle 1 1 100.00
pwm_rand_output 50.000s 0.000us 1 1 100.00
pulse 1 1 100.00
pwm_rand_output 50.000s 0.000us 1 1 100.00
blink 1 1 100.00
pwm_rand_output 50.000s 0.000us 1 1 100.00
heartbeat 1 1 100.00
pwm_rand_output 50.000s 0.000us 1 1 100.00
resolution 1 1 100.00
pwm_rand_output 50.000s 0.000us 1 1 100.00
multi_channel 1 1 100.00
pwm_rand_output 50.000s 0.000us 1 1 100.00
polarity 1 1 100.00
pwm_rand_output 50.000s 0.000us 1 1 100.00
phase 2 2 100.00
pwm_rand_output 50.000s 0.000us 1 1 100.00
pwm_phase 39.000s 0.000us 1 1 100.00
lowpower 1 1 100.00
pwm_rand_output 50.000s 0.000us 1 1 100.00
perf 1 1 100.00
pwm_perf 42.000s 0.000us 1 1 100.00
regwen 0 1 0.00
pwm_regwen 149.000s 0.000us 0 1 0.00
stress_all 1 1 100.00
pwm_stress_all 129.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
pwm_alert_test 2.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwm_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwm_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwm_csr_hw_reset 1.000s 0.000us 1 1 100.00
pwm_csr_rw 1.000s 0.000us 1 1 100.00
pwm_csr_aliasing 2.000s 0.000us 1 1 100.00
pwm_same_csr_outstanding 2.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwm_csr_hw_reset 1.000s 0.000us 1 1 100.00
pwm_csr_rw 1.000s 0.000us 1 1 100.00
pwm_csr_aliasing 2.000s 0.000us 1 1 100.00
pwm_same_csr_outstanding 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwm_sec_cm 2.000s 0.000us 1 1 100.00
pwm_tl_intg_err 3.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwm_tl_intg_err 3.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
heartbeat_wrap 1 1 100.00
pwm_heartbeat_wrap 45.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (pwm_scoreboard.sv:386) scoreboard [scoreboard]
pwm_regwen 51473580677267841515464379709221367472533925869360335590219776861598831671143 101
UVM_FATAL @ 10598748794 ps: (pwm_scoreboard.sv:386) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard]
PWM :: Channel = [3] did not MATCH
UVM_INFO @ 10598748794 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---