Simulation Results

Simulation Results: pwrmgr

24/03/2026 17:19:26 DVSim: v1.16.0 sha: 4125149 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
96.02 %

code
94.63 %

assert
96.08 %

func
97.36 %

line
98.92 %

branch
95.42 %

cond
94.77 %

toggle
90.02 %

FSM
94.00 %

Validation stages

V1		100.00%
V2		95.45%
V2S		52.94%
V3		50.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	pwrmgr_smoke	0.870s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	pwrmgr_csr_hw_reset	0.830s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	pwrmgr_csr_rw	0.660s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	pwrmgr_csr_bit_bash	2.700s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	pwrmgr_csr_aliasing	0.860s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	pwrmgr_csr_mem_rw_with_rand_reset	0.810s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	pwrmgr_csr_rw	0.660s	0.000us	1	1	100.00
	pwrmgr_csr_aliasing	0.860s	0.000us	1	1	100.00

21/22 passed

95.45 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wakeup				1	1	100.00
	pwrmgr_wakeup	0.890s	0.000us	1	1	100.00
control_clks				1	1	100.00
	pwrmgr_wakeup	0.890s	0.000us	1	1	100.00
aborted_low_power				2	2	100.00
	pwrmgr_aborted_low_power	0.910s	0.000us	1	1	100.00
	pwrmgr_lowpower_invalid	0.630s	0.000us	1	1	100.00
reset				2	2	100.00
	pwrmgr_reset	0.800s	0.000us	1	1	100.00
	pwrmgr_reset_invalid	0.760s	0.000us	1	1	100.00
main_power_glitch_reset				1	1	100.00
	pwrmgr_reset	0.800s	0.000us	1	1	100.00
reset_wakeup_race				1	1	100.00
	pwrmgr_wakeup_reset	0.860s	0.000us	1	1	100.00
lowpower_wakeup_race				1	1	100.00
	pwrmgr_lowpower_wakeup_race	0.960s	0.000us	1	1	100.00
disable_rom_integrity_check				1	1	100.00
	pwrmgr_disable_rom_integrity_check	0.940s	0.000us	1	1	100.00
stress_all				0	1	0.00
	pwrmgr_stress_all	8.790s	0.000us	0	1	0.00
intr_test				1	1	100.00
	pwrmgr_intr_test	0.620s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	pwrmgr_tl_errors	1.880s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	pwrmgr_tl_errors	1.880s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.830s	0.000us	1	1	100.00
	pwrmgr_csr_rw	0.660s	0.000us	1	1	100.00
	pwrmgr_csr_aliasing	0.860s	0.000us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.730s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	pwrmgr_csr_hw_reset	0.830s	0.000us	1	1	100.00
	pwrmgr_csr_rw	0.660s	0.000us	1	1	100.00
	pwrmgr_csr_aliasing	0.860s	0.000us	1	1	100.00
	pwrmgr_same_csr_outstanding	0.730s	0.000us	1	1	100.00

V2S

9/17 passed

52.94 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	2	0.00
	pwrmgr_sec_cm	0.740s	0.000us	0	1	0.00
	pwrmgr_tl_intg_err	0.670s	0.000us	0	1	0.00
prim_count_check				0	1	0.00
	pwrmgr_sec_cm	0.740s	0.000us	0	1	0.00
prim_fsm_check				0	1	0.00
	pwrmgr_sec_cm	0.740s	0.000us	0	1	0.00
sec_cm_bus_integrity				0	1	0.00
	pwrmgr_tl_intg_err	0.670s	0.000us	0	1	0.00
sec_cm_lc_ctrl_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	1.440s	0.000us	1	1	100.00
sec_cm_rom_ctrl_intersig_mubi				1	1	100.00
	pwrmgr_wakeup_reset	0.860s	0.000us	1	1	100.00
sec_cm_rstmgr_intersig_mubi				1	1	100.00
	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.840s	0.000us	1	1	100.00
sec_cm_esc_rx_clk_bkgn_chk				1	1	100.00
	pwrmgr_esc_clk_rst_malfunc	0.670s	0.000us	1	1	100.00
sec_cm_esc_rx_clk_local_esc				0	1	0.00
	pwrmgr_sec_cm	0.740s	0.000us	0	1	0.00
sec_cm_fsm_sparse				0	1	0.00
	pwrmgr_sec_cm	0.740s	0.000us	0	1	0.00
sec_cm_fsm_terminal				0	1	0.00
	pwrmgr_sec_cm	0.740s	0.000us	0	1	0.00
sec_cm_ctrl_flow_global_esc				1	1	100.00
	pwrmgr_global_esc	0.580s	0.000us	1	1	100.00
sec_cm_main_pd_rst_local_esc				1	1	100.00
	pwrmgr_glitch	0.570s	0.000us	1	1	100.00
sec_cm_ctrl_config_regwen				1	1	100.00
	pwrmgr_sec_cm_ctrl_config_regwen	0.850s	0.000us	1	1	100.00
sec_cm_wakeup_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.660s	0.000us	1	1	100.00
sec_cm_reset_config_regwen				1	1	100.00
	pwrmgr_csr_rw	0.660s	0.000us	1	1	100.00

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
escalation_timeout				0	1	0.00
	pwrmgr_escalation_timeout	0.770s	0.000us	0	1	0.00
stress_all_with_rand_reset				1	1	100.00
	pwrmgr_stress_all_with_rand_reset	11.120s	0.000us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A
	pwrmgr_escalation_timeout	40589716155419862994828852707955328337949218938307686252627062537748653984032	75	UVM_ERROR @ 175506798 ps: (pwrmgr_sec_cm_checker_assert.sv:166) [ASSERT FAILED] EscClkStopEscTimeout_A UVM_INFO @ 175506798 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
	pwrmgr_sec_cm	9393105375889817214692246397006694482019817311678604178426822519729853794131	86	UVM_ERROR @ 32962379 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 32962379 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	pwrmgr_tl_intg_err	70004340155464600332018952160761524683144848662552885277720719118524180707828	78	UVM_ERROR @ 8498923 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pwrmgr_common_vseq] expect alert:fatal_fault to fire UVM_INFO @ 8498923 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred!
	pwrmgr_stress_all	45114014633259827853186344450836349513884762993705482100958315874119011596772	413	UVM_FATAL @ 10651958240 ps: (pwrmgr_reset_vseq.sv:62) [uvm_test_top.env.virtual_sequencer.pwrmgr_reset_vseq] wait timeout occurred! UVM_INFO @ 10651958240 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---