Simulation Results

Simulation Results: rv_timer

24/03/2026 17:19:26 DVSim: v1.16.0 sha: 4125149 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
95.16 %

code
99.53 %

assert
96.82 %

func
89.12 %

line
99.64 %

branch
100.00 %

cond
98.46 %

toggle
100.00 %

Validation stages

V1		100.00%
V2		94.12%
V2S		100.00%
V3		0.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
random				1	1	100.00
	rv_timer_random	0.870s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	rv_timer_csr_hw_reset	0.670s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	rv_timer_csr_rw	0.580s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	rv_timer_csr_bit_bash	1.390s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	rv_timer_csr_aliasing	0.820s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	rv_timer_csr_mem_rw_with_rand_reset	0.730s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	rv_timer_csr_rw	0.580s	0.000us	1	1	100.00
	rv_timer_csr_aliasing	0.820s	0.000us	1	1	100.00

16/17 passed

94.12 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
random_reset				0	1	0.00
	rv_timer_random_reset	1.080s	0.000us	0	1	0.00
disabled				1	1	100.00
	rv_timer_disabled	1.280s	0.000us	1	1	100.00
cfg_update_on_fly				1	1	100.00
	rv_timer_cfg_update_on_fly	104.870s	0.000us	1	1	100.00
no_interrupt_test				1	1	100.00
	rv_timer_cfg_update_on_fly	104.870s	0.000us	1	1	100.00
stress				1	1	100.00
	rv_timer_stress_all	1.600s	0.000us	1	1	100.00
alert_test				1	1	100.00
	rv_timer_alert_test	0.850s	0.000us	1	1	100.00
intr_test				1	1	100.00
	rv_timer_intr_test	0.540s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	rv_timer_tl_errors	2.150s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	rv_timer_tl_errors	2.150s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	rv_timer_csr_hw_reset	0.670s	0.000us	1	1	100.00
	rv_timer_csr_rw	0.580s	0.000us	1	1	100.00
	rv_timer_csr_aliasing	0.820s	0.000us	1	1	100.00
	rv_timer_same_csr_outstanding	0.680s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	rv_timer_csr_hw_reset	0.670s	0.000us	1	1	100.00
	rv_timer_csr_rw	0.580s	0.000us	1	1	100.00
	rv_timer_csr_aliasing	0.820s	0.000us	1	1	100.00
	rv_timer_same_csr_outstanding	0.680s	0.000us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	rv_timer_sec_cm	1.040s	0.000us	1	1	100.00
	rv_timer_tl_intg_err	1.200s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	rv_timer_tl_intg_err	1.200s	0.000us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
min_value				1
	rv_timer_min	0.720s	0.000us	1
max_value				1
	rv_timer_max	0.700s	0.000us	1
stress_all_with_rand_reset				1
	rv_timer_stress_all_with_rand_reset	16.780s	0.000us	1

Error Messages

	Test	seed	line	log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=) ==
	rv_timer_min	102622870419170723064016277729820530063457574894290166856429819274756198465596	75	UVM_FATAL @ 78245114 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xd958c104) == 0x1 UVM_INFO @ 78245114 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rv_timer_random_reset	51815309374424210720520395228095463299753648814622462656720299401386974118283	76	UVM_FATAL @ 227250989 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xa7b54b04) == 0x1 UVM_INFO @ 227250989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs [*])
	rv_timer_max	113504169853154753204637786243825523775604783988971445655936291211636074899751	75	UVM_ERROR @ 42720350 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0]) UVM_INFO @ 42720350 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done)
	rv_timer_stress_all_with_rand_reset	32911829184008290403690339248735502201633119786923633968476402537489541890262	293	UVM_FATAL @ 6385944861 ps: (cip_base_vseq.sv:1170) [uvm_test_top.env.virtual_sequencer.rv_timer_common_vseq] Check failed (vseq_done) UVM_INFO @ 6385944861 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---