Simulation Results: spi_device/2p

 
24/03/2026 17:19:26 DVSim: v1.16.0 sha: 4125149 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.19 %
  • code
  • 94.18 %
  • assert
  • 94.62 %
  • func
  • 78.77 %
  • line
  • 99.13 %
  • branch
  • 98.40 %
  • cond
  • 96.28 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 27.210s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.020s 0.000us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.650s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 7.560s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 5.220s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 3.030s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.650s 0.000us 1 1 100.00
spi_device_csr_aliasing 5.220s 0.000us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.820s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.410s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.980s 0.000us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.280s 0.000us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.990s 0.000us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.030s 0.000us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.030s 0.000us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 3.990s 0.000us 1 1 100.00
spi_device_tpm_sts_read 1.050s 0.000us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 22.370s 0.000us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 7.190s 0.000us 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.490s 0.000us 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.490s 0.000us 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 3.650s 0.000us 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 3.650s 0.000us 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 3.650s 0.000us 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 3.650s 0.000us 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 3.650s 0.000us 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 2.270s 0.000us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 3.070s 0.000us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 3.070s 0.000us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 3.070s 0.000us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 9.870s 0.000us 1 1 100.00
spi_device_read_buffer_direct 5.760s 0.000us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 3.070s 0.000us 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 89.300s 0.000us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.010s 0.000us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.010s 0.000us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 27.210s 0.000us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 125.850s 0.000us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 186.750s 0.000us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.830s 0.000us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.690s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.970s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.970s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 0.000us 1 1 100.00
spi_device_csr_rw 1.650s 0.000us 1 1 100.00
spi_device_csr_aliasing 5.220s 0.000us 1 1 100.00
spi_device_same_csr_outstanding 2.160s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.020s 0.000us 1 1 100.00
spi_device_csr_rw 1.650s 0.000us 1 1 100.00
spi_device_csr_aliasing 5.220s 0.000us 1 1 100.00
spi_device_same_csr_outstanding 2.160s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_tl_intg_err 13.330s 0.000us 1 1 100.00
spi_device_sec_cm 1.140s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 13.330s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 43.300s 0.000us 1 1 100.00