Simulation Results: spi_host

 
24/03/2026 17:19:26 DVSim: v1.16.0 sha: 4125149 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.33 %
  • code
  • 95.03 %
  • assert
  • 94.13 %
  • func
  • 87.82 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
96.67%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 64.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 2.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 2.000s 0.000us 1 1 100.00
spi_host_csr_aliasing 2.000s 0.000us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 0.000us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 13.000s 0.000us 1 1 100.00
spi_host_error_cmd 1.000s 0.000us 1 1 100.00
spi_host_event 179.000s 0.000us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 0.000us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 0.000us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 0.000us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 13.000s 0.000us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 0.000us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 0.000us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 0.000us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 64.000s 0.000us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 64.000s 0.000us 1 1 100.00
stress_all 0 1 0.00
spi_host_stress_all 1450.000s 0.000us 0 1 0.00
spien 1 1 100.00
spi_host_spien 6.000s 0.000us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 86.000s 0.000us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 0.000us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 13.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 0.000us 1 1 100.00
spi_host_csr_rw 2.000s 0.000us 1 1 100.00
spi_host_csr_aliasing 2.000s 0.000us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 0.000us 1 1 100.00
spi_host_csr_rw 2.000s 0.000us 1 1 100.00
spi_host_csr_aliasing 2.000s 0.000us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_sec_cm 2.000s 0.000us 1 1 100.00
spi_host_tl_intg_err 1.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 1.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 42.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_host_stress_all 36387931719031076161766233089329107777073161545023849475384720026972527897097 268
UVM_FATAL @ 1000000000000 ps: (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of 1000000000000 ps hit, indicating a probable testbench issue
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---