Simulation Results: uart

 
24/03/2026 17:19:26 DVSim: v1.16.0 sha: 4125149 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.61 %
  • code
  • 96.25 %
  • assert
  • 97.12 %
  • func
  • 54.46 %
  • line
  • 99.17 %
  • branch
  • 97.20 %
  • cond
  • 97.08 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 9.920s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.550s 0.000us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.580s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.180s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.710s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.840s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.580s 0.000us 1 1 100.00
uart_csr_aliasing 0.710s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 23.360s 0.000us 1 1 100.00
parity 2 2 100.00
uart_smoke 9.920s 0.000us 1 1 100.00
uart_tx_rx 23.360s 0.000us 1 1 100.00
parity_error 2 2 100.00
uart_intr 12.480s 0.000us 1 1 100.00
uart_rx_parity_err 12.970s 0.000us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 23.360s 0.000us 1 1 100.00
uart_intr 12.480s 0.000us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 193.930s 0.000us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 103.310s 0.000us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 26.120s 0.000us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 12.480s 0.000us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 12.480s 0.000us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 12.480s 0.000us 1 1 100.00
perf 1 1 100.00
uart_perf 540.470s 0.000us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 3.710s 0.000us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 3.710s 0.000us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 8.890s 0.000us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 55.500s 0.000us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 7.290s 0.000us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 10.410s 0.000us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 147.280s 0.000us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 142.620s 0.000us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.640s 0.000us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.560s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.400s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.400s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.550s 0.000us 1 1 100.00
uart_csr_rw 0.580s 0.000us 1 1 100.00
uart_csr_aliasing 0.710s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.600s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.550s 0.000us 1 1 100.00
uart_csr_rw 0.580s 0.000us 1 1 100.00
uart_csr_aliasing 0.710s 0.000us 1 1 100.00
uart_same_csr_outstanding 0.600s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.810s 0.000us 1 1 100.00
uart_tl_intg_err 1.130s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.130s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 45.030s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_noise_filter 97191586324588059079664915909662414652204779303139032844665207617447845427055 74
UVM_ERROR @ 184770486 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 3, clk_pulses: 0
UVM_ERROR @ 184806200 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 185020484 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 251 [0xfb]) reg name: uart_reg_block.rdata
UVM_ERROR @ 288948224 ps: (uart_scoreboard.sv:445) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp_at_addr_phase[i] (1 [0x1] vs 0 [0x0]) Interrupt: RxWatermark
UVM_ERROR @ 288948224 ps: (uart_scoreboard.sv:447) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (0x1 [1] vs 0x0 [0]) Interrupt_pin: RxWatermark