Simulation Results: adc_ctrl

 
25/03/2026 17:18:13 DVSim: v1.16.0 sha: 373d38a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.09 %
  • code
  • 96.35 %
  • assert
  • 95.62 %
  • func
  • 18.31 %
  • line
  • 99.02 %
  • branch
  • 97.71 %
  • cond
  • 93.13 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 6.290s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.630s 0.000us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.950s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 9.960s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 3.270s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.570s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.950s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 3.270s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 86.370s 0.000us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 245.700s 0.000us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 299.070s 0.000us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 573.180s 0.000us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 208.460s 0.000us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 161.910s 0.000us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 609.340s 0.000us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 593.190s 0.000us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 3.080s 0.000us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 8.510s 0.000us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 45.870s 0.000us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 99.690s 0.000us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.830s 0.000us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.680s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.880s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.880s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.630s 0.000us 1 1 100.00
adc_ctrl_csr_rw 0.950s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 3.270s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.620s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.630s 0.000us 1 1 100.00
adc_ctrl_csr_rw 0.950s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 3.270s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 4.620s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 4.720s 0.000us 1 1 100.00
adc_ctrl_sec_cm 12.890s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 4.720s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 12.140s 0.000us 1 1 100.00