Simulation Results: chip

 
25/03/2026 17:18:13 DVSim: v1.16.0 sha: 373d38a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 77.60 %
  • code
  • 85.05 %
  • assert
  • 97.37 %
  • func
  • 50.39 %
  • line
  • 94.27 %
  • branch
  • 93.58 %
  • cond
  • 89.14 %
  • toggle
  • 91.13 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
85.29%
V2S
100.00%
V3
60.00%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 148.350s 0.000us 1 1 100.00
chip_sw_example_rom 71.810s 0.000us 1 1 100.00
chip_sw_example_manufacturer 107.920s 0.000us 1 1 100.00
chip_sw_example_concurrency 146.940s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 241.460s 0.000us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 259.980s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 3052.130s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4249.710s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 284.720s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4249.710s 0.000us 1 1 100.00
chip_csr_rw 259.980s 0.000us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 7.230s 0.000us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 312.630s 0.000us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 312.630s 0.000us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 312.630s 0.000us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 398.700s 0.000us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 398.700s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx1 353.510s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx2 369.830s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx3 349.260s 0.000us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 984.680s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 380.400s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 247.220s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 204.920s 0.000us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 204.920s 0.000us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 176.170s 0.000us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 349.870s 0.000us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 200.810s 0.000us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 1348.080s 0.000us 1 1 100.00
chip_tap_straps_testunlock0 396.200s 0.000us 1 1 100.00
chip_tap_straps_rma 85.420s 0.000us 1 1 100.00
chip_tap_straps_prod 550.890s 0.000us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 203.320s 0.000us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 777.450s 0.000us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 387.460s 0.000us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 387.460s 0.000us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 687.050s 0.000us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 899.670s 0.000us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 329.760s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 539.440s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3438.650s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 151.470s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 579.810s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 180.850s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1236.800s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 159.150s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 376.260s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 178.360s 0.000us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 191.840s 0.000us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 255.980s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 286.960s 0.000us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 129.450s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 286.960s 0.000us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 191.390s 0.000us 1 1 100.00
chip_sw_aes_smoketest 164.520s 0.000us 1 1 100.00
chip_sw_aon_timer_smoketest 142.200s 0.000us 1 1 100.00
chip_sw_clkmgr_smoketest 135.900s 0.000us 1 1 100.00
chip_sw_csrng_smoketest 142.460s 0.000us 1 1 100.00
chip_sw_entropy_src_smoketest 811.000s 0.000us 1 1 100.00
chip_sw_gpio_smoketest 167.220s 0.000us 1 1 100.00
chip_sw_hmac_smoketest 201.780s 0.000us 1 1 100.00
chip_sw_kmac_smoketest 160.410s 0.000us 1 1 100.00
chip_sw_otbn_smoketest 669.990s 0.000us 1 1 100.00
chip_sw_pwrmgr_smoketest 199.150s 0.000us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 268.910s 0.000us 1 1 100.00
chip_sw_rv_plic_smoketest 158.360s 0.000us 1 1 100.00
chip_sw_rv_timer_smoketest 137.700s 0.000us 1 1 100.00
chip_sw_rstmgr_smoketest 95.570s 0.000us 1 1 100.00
chip_sw_sram_ctrl_smoketest 116.570s 0.000us 1 1 100.00
chip_sw_uart_smoketest 155.050s 0.000us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 151.990s 0.000us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 400.630s 0.000us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7934.530s 0.000us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2564.480s 0.000us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 130.810s 0.000us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 236.730s 0.000us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 200.340s 0.000us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6645.080s 0.000us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7445.630s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 58.700s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 58.700s 0.000us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4249.710s 0.000us 1 1 100.00
chip_same_csr_outstanding 1014.250s 0.000us 1 1 100.00
chip_csr_hw_reset 241.460s 0.000us 1 1 100.00
chip_csr_rw 259.980s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4249.710s 0.000us 1 1 100.00
chip_same_csr_outstanding 1014.250s 0.000us 1 1 100.00
chip_csr_hw_reset 241.460s 0.000us 1 1 100.00
chip_csr_rw 259.980s 0.000us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 5.840s 0.000us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.210s 0.000us 1 1 100.00
xbar_smoke_large_delays 59.150s 0.000us 1 1 100.00
xbar_smoke_slow_rsp 29.740s 0.000us 1 1 100.00
xbar_random_zero_delays 6.140s 0.000us 1 1 100.00
xbar_random_large_delays 307.510s 0.000us 1 1 100.00
xbar_random_slow_rsp 27.850s 0.000us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 28.910s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 31.900s 0.000us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 31.170s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 31.900s 0.000us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 53.160s 0.000us 1 1 100.00
xbar_access_same_device_slow_rsp 639.490s 0.000us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 16.680s 0.000us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 98.210s 0.000us 1 1 100.00
xbar_stress_all_with_error 307.160s 0.000us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 197.110s 0.000us 1 1 100.00
xbar_stress_all_with_reset_error 190.080s 0.000us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2564.480s 0.000us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2438.910s 0.000us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2362.900s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2132.000s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2693.220s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2613.430s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2618.200s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2465.490s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 17.120s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 33.340s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 21.690s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 20.600s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 17.410s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 16.510s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 17.720s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 16.920s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 16.270s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 16.410s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 17.270s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 17.390s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.830s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 19.550s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 17.930s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 20.950s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 17.710s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 17.610s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 17.790s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.730s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.040s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.270s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 18.990s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.920s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 17.760s 0.000us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2004.490s 0.000us 1 1 100.00
rom_e2e_asm_init_dev 2500.260s 0.000us 1 1 100.00
rom_e2e_asm_init_prod 2526.420s 0.000us 1 1 100.00
rom_e2e_asm_init_prod_end 2434.690s 0.000us 1 1 100.00
rom_e2e_asm_init_rma 2403.640s 0.000us 1 1 100.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 2444.190s 0.000us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_no_meas 4223.110s 0.000us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 4419.100s 0.000us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2576.840s 0.000us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2900.500s 0.000us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2900.500s 0.000us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 151.020s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 151.470s 0.000us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 173.720s 0.000us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 145.430s 0.000us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1185.600s 0.000us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 150.060s 0.000us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 316.770s 0.000us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 373.600s 0.000us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 500.950s 0.000us 1 1 100.00
chip_plic_all_irqs_10 289.780s 0.000us 1 1 100.00
chip_plic_all_irqs_20 350.260s 0.000us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 238.480s 0.000us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1102.580s 0.000us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 243.190s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 170.470s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1226.210s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 885.220s 0.000us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 850.620s 0.000us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 8414.060s 0.000us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 242.890s 0.000us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 199.150s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 242.890s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 476.850s 0.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_bite_reset 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 476.850s 0.000us 0 1 0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 305.640s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 315.510s 0.000us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 561.290s 0.000us 1 1 100.00
chip_sw_aes_idle 145.430s 0.000us 1 1 100.00
chip_sw_hmac_enc_idle 163.840s 0.000us 1 1 100.00
chip_sw_kmac_idle 125.280s 0.000us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 211.530s 0.000us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 283.400s 0.000us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 293.700s 0.000us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 366.250s 0.000us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 715.840s 0.000us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 428.170s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 397.360s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 363.800s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 382.940s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 425.650s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 366.720s 0.000us 1 1 100.00
chip_sw_ast_clk_outputs 687.050s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 531.510s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 363.800s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 382.940s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 329.760s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 539.440s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3438.650s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 151.470s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 579.810s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 180.850s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1236.800s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 159.150s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 376.260s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 178.360s 0.000us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 143.450s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 403.440s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 612.010s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3146.530s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 175.760s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 188.560s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 1074.790s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 189.270s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 405.040s 0.000us 1 1 100.00
chip_sw_flash_init_reduced_freq 1122.020s 0.000us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 3143.500s 0.000us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 687.050s 0.000us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 334.690s 0.000us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 270.550s 0.000us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 373.600s 0.000us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1226.210s 0.000us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 904.800s 0.000us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 191.720s 0.000us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 492.190s 0.000us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 177.000s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3694.790s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 156.580s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 771.840s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 156.580s 0.000us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 904.800s 0.000us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 145.460s 0.000us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1345.390s 0.000us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 600.760s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 539.440s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 415.720s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 329.760s 0.000us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3146.640s 0.000us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1345.390s 0.000us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 183.390s 0.000us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1072.110s 0.000us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 133.710s 0.000us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3146.640s 0.000us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 133.710s 0.000us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 133.710s 0.000us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 133.710s 0.000us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 133.710s 0.000us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 373.600s 0.000us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 80.810s 0.000us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 564.670s 0.000us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 429.830s 0.000us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 429.830s 0.000us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 185.180s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 180.850s 0.000us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 163.840s 0.000us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 931.910s 0.000us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 683.870s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 387.170s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 377.200s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 362.880s 0.000us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 276.750s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1072.110s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1236.800s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1256.490s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1185.600s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2046.380s 0.000us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 158.100s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac 177.070s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 159.150s 0.000us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1072.110s 0.000us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 558.880s 0.000us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 128.680s 0.000us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1265.060s 0.000us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 125.280s 0.000us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 316.770s 0.000us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 1348.080s 0.000us 1 1 100.00
chip_tap_straps_rma 85.420s 0.000us 1 1 100.00
chip_tap_straps_prod 550.890s 0.000us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 187.170s 0.000us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 558.880s 0.000us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 558.880s 0.000us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 558.880s 0.000us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 829.540s 0.000us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_prim_tl_access 80.810s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 166.580s 0.000us 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 133.710s 0.000us 0 1 0.00
chip_sw_flash_rma_unlocked 3146.640s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 188.540s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 604.600s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 636.760s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 563.070s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 558.880s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1072.110s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 334.000s 0.000us 1 1 100.00
chip_sw_sram_ctrl_execution_main 635.960s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 531.510s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 428.170s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 397.360s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 363.800s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 382.940s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 425.650s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 366.720s 0.000us 1 1 100.00
chip_tap_straps_dev 1348.080s 0.000us 1 1 100.00
chip_tap_straps_rma 85.420s 0.000us 1 1 100.00
chip_tap_straps_prod 550.890s 0.000us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 139.940s 0.000us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 83.870s 0.000us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 72.970s 0.000us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 106.580s 0.000us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_rv_dm_lc_disabled 166.580s 0.000us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1648.160s 0.000us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 586.610s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prod 635.450s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prodend 588.310s 0.000us 1 1 100.00
chip_sw_lc_walkthrough_rma 320.690s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1648.160s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 67.010s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 78.440s 0.000us 1 1 100.00
rom_volatile_raw_unlock 71.540s 0.000us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3579.960s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3438.650s 0.000us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 561.290s 0.000us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 561.290s 0.000us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 561.290s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 305.440s 0.000us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 558.880s 0.000us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1345.390s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 305.440s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1072.110s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 405.720s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 182.030s 0.000us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1345.390s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 305.440s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1072.110s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 405.720s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 182.030s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 558.880s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 357.920s 0.000us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 187.170s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 80.810s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 188.540s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 604.600s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 636.760s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 563.070s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 558.880s 0.000us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 80.810s 0.000us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 906.380s 0.000us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 294.940s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1069.970s 0.000us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 181.320s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 321.220s 0.000us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 546.390s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1102.630s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 0 2 0.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 432.640s 0.000us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 476.850s 0.000us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 947.020s 0.000us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 365.320s 0.000us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 294.940s 0.000us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 189.210s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1722.320s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 327.460s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 275.260s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1293.060s 0.000us 1 1 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 748.570s 0.000us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 993.920s 0.000us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1899.860s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 163.700s 0.000us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 373.600s 0.000us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 334.000s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 334.000s 0.000us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 4 4 100.00
chip_sw_pwrmgr_all_reset_reqs 993.920s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 1293.060s 0.000us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 365.320s 0.000us 1 1 100.00
chip_sw_pwrmgr_smoketest 199.150s 0.000us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 309.750s 0.000us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 303.310s 0.000us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 240.410s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1102.580s 0.000us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 147.420s 0.000us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 373.600s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 885.220s 0.000us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 474.250s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 561.840s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 213.780s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 182.030s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 303.310s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 303.310s 0.000us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 623.650s 0.000us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 899.230s 0.000us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 309.750s 0.000us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 213.600s 0.000us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 298.510s 0.000us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 85.420s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 166.580s 0.000us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 500.950s 0.000us 1 1 100.00
chip_plic_all_irqs_10 289.780s 0.000us 1 1 100.00
chip_plic_all_irqs_20 350.260s 0.000us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 152.170s 0.000us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 174.770s 0.000us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2564.480s 0.000us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 521.500s 0.000us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 213.670s 0.000us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 228.150s 0.000us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 197.900s 0.000us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 405.720s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 376.260s 0.000us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 484.050s 0.000us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 380.870s 0.000us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 635.960s 0.000us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 373.600s 0.000us 1 1 100.00
chip_sw_data_integrity_escalation 387.460s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 748.570s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1028.820s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 158.800s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 239.280s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 309.920s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1028.820s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1028.820s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2307.570s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2307.570s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 378.460s 0.000us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2900.500s 0.000us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 144.430s 0.000us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 125.080s 0.000us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 266.810s 0.000us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 386.300s 0.000us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1095.590s 0.000us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4836.350s 0.000us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1833.500s 0.000us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 180.840s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 152.340s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 98.940s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 9116.540s 0.000us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 998.620s 0.000us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 410.310s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 133.020s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 431.930s 0.000us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 51.190s 0.000us 0 1 0.00
rom_e2e_jtag_inject_dev 74.470s 0.000us 0 1 0.00
rom_e2e_jtag_inject_rma 70.370s 0.000us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 8.206s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 305.920s 0.000us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 311.800s 0.000us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 699.090s 0.000us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 974.440s 0.000us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 208.600s 0.000us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 585.000s 0.000us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 163.150s 0.000us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 155.210s 0.000us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 280.710s 0.000us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 251.230s 0.000us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 993.920s 0.000us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 410.310s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 133.020s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 431.930s 0.000us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 392.590s 0.000us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 373.600s 0.000us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5081.490s 0.000us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5081.490s 0.000us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 211.500s 0.000us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 398.700s 0.000us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3091.100s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 178.470s 0.000us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 424.480s 0.000us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.640s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 167.680s 0.000us 1 1 100.00
chip_sw_otp_ctrl_descrambling 228.230s 0.000us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 194.680s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 8.166s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 199.150s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 46448269589264675471652777855331152378853451496405331827228246948690869185965 217
UVM_ERROR @ 2298.146792 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@37515) { a_addr: 'h10568 a_data: 'h21b67bad a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h2 a_opcode: 'h4 a_user: 'h1b616 d_param: 'h0 d_source: 'h2 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2298.146792 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 28807592065541562359405948543810290568429210313954435902817552933870206359507 333
UVM_ERROR @ 4863.061469 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@128755) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 4863.061469 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 79555662893123708197608515846409571063650406104864289282917866892757257839269 320
UVM_ERROR @ 3180.476055 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3180.476055 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 57859676677307419882681175176510342308118431709232673531094128376573796186942 309
UVM_ERROR @ 2682.516524 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 2682.516524 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 9615128343197975849874845882457465817293657545448322607806024360650674502468 342
UVM_ERROR @ 5997.741216 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 5997.741216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 16420456755628012192588476914043490544941706451900935046316314717991957141651 316
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2932.516224 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2932.516224 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 909553979228118622534863136288859336379951983432942265531904662147714648913 312
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2825.566470 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2825.566470 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 108660657852579095278729282379056048830364679281009960695885712659636401628923 282
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 11535425632937224265864346117027474275495120336542652280146100460082046061510 369
UVM_ERROR @ 11067.151410 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 11067.151410 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 25318810407959079512193694875955870929165547967260435787262040521265371735717 369
UVM_ERROR @ 8773.923592 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 8773.923592 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 79148745016886589267549841769911912354161823254506255322165026582970421887700 341
UVM_ERROR @ 5835.071264 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 5835.071264 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 73215966760849916538706477236702385663053249896590648998505033438308009674601 327
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 9934.875000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 9934.875000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 57628465872603472483710486676902235208532723646777010629783245180860216480493 325
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7463.237000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7463.237000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_aon_timer_wdog_bite_reset 104414996445755696545821191304472993459274412396382498737953036016377801881237 319
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 7451.180000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7451.180000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 80324273107232467605312450770863305926405932285430401812051678913366596848822 332
UVM_ERROR @ 34527.345011 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34527.345011 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:412)] CHECK-fail: Expect alert *!
chip_sw_alert_test 113097574514391053689331918026283797210160272588676239091759307095305019374994 307
UVM_ERROR @ 2573.920994 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:412)] CHECK-fail: Expect alert 37!
UVM_INFO @ 2573.920994 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 47548999065447335336602129621948668124290855709587217624466460775719788036412 308
UVM_ERROR @ 3621.877140 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3621.877140 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 89686770242593637895771560577220088838816775749044222282215515386217625809704 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 8402272522622533297850026022906534003534125900680701764639713929848956039334 343
UVM_ERROR @ 4475.010724 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 4475.010724 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 55226784509849135490637089002216179558500900592878130209818956865196991594124 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 65445964736676837080173305223153821453100420137352869985009463661726141210160 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 9005982707927847111991759919802989907101110609879686949282539595337369070396 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 110465074110722108609861926069690451639915739165986162395006559730178409706889 352
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 90198710333997381900899003059969827571424675382239022578644247640114096390209 352
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 83181600430550277092969030505871822179858604975254142972768835592033409428091 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 65711894059300003281059644943896315531499204469502091468609270818415383582787 307
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 43581089048395282543158254863572676369238522079632516822085459413293405117079 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 71535494306381349180634465192878161362405091675781799604022139022407599962394 312
UVM_ERROR @ 3789.146000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3789.146000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 46640157518702353006871482201976635870703777924228319823606643134879127154745 319
UVM_ERROR @ 3288.282500 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3288.282500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 94923846745181462565381189160331679890450435718180149339292106401873170329438 327
UVM_ERROR @ 11111.681572 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 11111.681572 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 66942786015253912495358412603855890652302349843500104772760160265655117751098 351
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 66305307049653944542765867187457706089802308763369609991933628002610516535295 348
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 88389007256217683963774824082780686647626360797488594890468656507439148491897 351
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 100279222071099948802206253428578896794794809310423631388496983939548127638400 351
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 90692265644347820465325442019504157714932103434566983762670621597256919919089 351
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 21962454073993659317642879476955485899263949488296664556378433294439775416095 349
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 62233719409064165688690959733018614768659592119926355286016402246385801157298 348
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 27654067303963910934385305692020912046644183063887653794865567619615684646332 348
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 113562784980371780315170777819813253626927196993710721180408713040434768383347 349
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 100631102788597513798857467860832006483050643040431839071413636831559579992754 349
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 106189268339804593898494093339057407124980368385928819920532580237673164049700 362
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 100289706712453588891163850308492554620487195202612867963208961916080674872201 360
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 75352541856418622921779487922372107354395538498957348042534316311221965854486 358
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 19555068665680012487119332265815738477177723076120476255337484164216104561310 322
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 15276245821465265302935193492012428284074369069814860769125127514974300282174 325
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 45449890193952664457882136326561906676103355901644925843550222936033315917425 323
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 13493961061619531422657088343551383465321152359525233036470038932593034414279 359
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 24430439696048862222267921251586020022093399234078939883270032970637488505955 323
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 42918482163127602852833099085585032106749308432220420439853179477596489297547 362
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 102835285878124308524266729910004753448164559653383111608702531941016240165992 324
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 24562608558259945169166668847956392077885605450105919596800621170025572714326 324
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 50713371612404501610827733703512890107067506360500702671264395048790192145772 324
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 103351387324181427580399593278734171762652616391371208349621023388974992822430 323
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 88685105586607472263240675876038828075331687149414798964220918098603272058845 323
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 113932586529457587920754940673600181482891075089739672733346893551249353776962 323
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (* [*] vs * [*])
rom_e2e_jtag_debug_dev 78417963140732625733029885101790164757853384866595552160707493863266112982873 317
UVM_ERROR @ 4097.296485 us: (jtag_rv_debugger.sv:613) [debugger] Check failed dcsr.cause == exp_debug_cause (0 [0x0] vs 2 [0x2])
UVM_INFO @ 4097.296485 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_meas 81163509579751034064749551088520010888057502572140198225915820376926673603559 319
UVM_ERROR @ 16570.480909 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 16570.480909 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 105490358351460905226470435860813077716625421448479982125960616928951239666763 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 4778.404372 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4778.404372 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---