Simulation Results: hmac

 
25/03/2026 17:18:13 DVSim: v1.16.0 sha: 373d38a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.55 %
  • code
  • 96.02 %
  • assert
  • 96.70 %
  • func
  • 42.94 %
  • line
  • 99.12 %
  • branch
  • 97.69 %
  • cond
  • 95.05 %
  • toggle
  • 100.00 %
  • FSM
  • 88.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.180s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.850s 0.000us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.770s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 4.190s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.110s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.080s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.770s 0.000us 1 1 100.00
hmac_csr_aliasing 4.110s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 28.230s 0.000us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 24.340s 0.000us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 178.880s 0.000us 1 1 100.00
hmac_test_sha384_vectors 19.760s 0.000us 1 1 100.00
hmac_test_sha512_vectors 370.980s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 7.030s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 6.250s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 10.600s 0.000us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 3.010s 0.000us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 454.880s 0.000us 1 1 100.00
error 1 1 100.00
hmac_error 17.890s 0.000us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 7.160s 0.000us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.180s 0.000us 1 1 100.00
hmac_long_msg 28.230s 0.000us 1 1 100.00
hmac_back_pressure 24.340s 0.000us 1 1 100.00
hmac_datapath_stress 454.880s 0.000us 1 1 100.00
hmac_burst_wr 3.010s 0.000us 1 1 100.00
hmac_stress_all 112.010s 0.000us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.180s 0.000us 1 1 100.00
hmac_long_msg 28.230s 0.000us 1 1 100.00
hmac_back_pressure 24.340s 0.000us 1 1 100.00
hmac_datapath_stress 454.880s 0.000us 1 1 100.00
hmac_wipe_secret 7.160s 0.000us 1 1 100.00
hmac_test_sha256_vectors 178.880s 0.000us 1 1 100.00
hmac_test_sha384_vectors 19.760s 0.000us 1 1 100.00
hmac_test_sha512_vectors 370.980s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 7.030s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 6.250s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 10.600s 0.000us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.180s 0.000us 1 1 100.00
hmac_long_msg 28.230s 0.000us 1 1 100.00
hmac_back_pressure 24.340s 0.000us 1 1 100.00
hmac_datapath_stress 454.880s 0.000us 1 1 100.00
hmac_burst_wr 3.010s 0.000us 1 1 100.00
hmac_error 17.890s 0.000us 1 1 100.00
hmac_wipe_secret 7.160s 0.000us 1 1 100.00
hmac_test_sha256_vectors 178.880s 0.000us 1 1 100.00
hmac_test_sha384_vectors 19.760s 0.000us 1 1 100.00
hmac_test_sha512_vectors 370.980s 0.000us 1 1 100.00
hmac_test_hmac256_vectors 7.030s 0.000us 1 1 100.00
hmac_test_hmac384_vectors 6.250s 0.000us 1 1 100.00
hmac_test_hmac512_vectors 10.600s 0.000us 1 1 100.00
hmac_stress_all 112.010s 0.000us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 112.010s 0.000us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.660s 0.000us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.690s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.380s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.380s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.850s 0.000us 1 1 100.00
hmac_csr_rw 0.770s 0.000us 1 1 100.00
hmac_csr_aliasing 4.110s 0.000us 1 1 100.00
hmac_same_csr_outstanding 1.060s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.850s 0.000us 1 1 100.00
hmac_csr_rw 0.770s 0.000us 1 1 100.00
hmac_csr_aliasing 4.110s 0.000us 1 1 100.00
hmac_same_csr_outstanding 1.060s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.200s 0.000us 1 1 100.00
hmac_tl_intg_err 3.110s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.110s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.180s 0.000us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.960s 0.000us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 45.410s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.450s 0.000us 1 1 100.00