Simulation Results: i2c

 
25/03/2026 17:18:13 DVSim: v1.16.0 sha: 373d38a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.67 %
  • code
  • 81.64 %
  • assert
  • 96.19 %
  • func
  • 79.18 %
  • line
  • 96.41 %
  • branch
  • 92.41 %
  • cond
  • 85.31 %
  • toggle
  • 89.45 %
  • FSM
  • 44.64 %
Validation stages
V1
100.00%
V2
91.84%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 1 1 100.00
i2c_host_smoke 15.420s 0.000us 1 1 100.00
target_smoke 1 1 100.00
i2c_target_smoke 10.650s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
i2c_csr_hw_reset 0.720s 0.000us 1 1 100.00
csr_rw 1 1 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
i2c_csr_bit_bash 2.010s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
i2c_csr_aliasing 0.940s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
i2c_csr_mem_rw_with_rand_reset 1.050s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
i2c_csr_aliasing 0.940s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 1 0.00
i2c_host_error_intr 0.770s 0.000us 0 1 0.00
host_stress_all 0 1 0.00
i2c_host_stress_all 996.730s 0.000us 0 1 0.00
host_maxperf 1 1 100.00
i2c_host_perf 236.080s 0.000us 1 1 100.00
host_override 1 1 100.00
i2c_host_override 0.640s 0.000us 1 1 100.00
host_fifo_watermark 1 1 100.00
i2c_host_fifo_watermark 46.250s 0.000us 1 1 100.00
host_fifo_overflow 1 1 100.00
i2c_host_fifo_overflow 83.100s 0.000us 1 1 100.00
host_fifo_reset 3 3 100.00
i2c_host_fifo_reset_fmt 0.950s 0.000us 1 1 100.00
i2c_host_fifo_fmt_empty 19.260s 0.000us 1 1 100.00
i2c_host_fifo_reset_rx 5.860s 0.000us 1 1 100.00
host_fifo_full 1 1 100.00
i2c_host_fifo_full 44.220s 0.000us 1 1 100.00
host_timeout 1 1 100.00
i2c_host_stretch_timeout 7.810s 0.000us 1 1 100.00
i2c_host_mode_toggle 1 1 100.00
i2c_host_mode_toggle 1.400s 0.000us 1 1 100.00
target_glitch 0 1 0.00
i2c_target_glitch 2.200s 0.000us 0 1 0.00
target_stress_all 1 1 100.00
i2c_target_stress_all 20.390s 0.000us 1 1 100.00
target_maxperf 1 1 100.00
i2c_target_perf 4.280s 0.000us 1 1 100.00
target_fifo_empty 2 2 100.00
i2c_target_stress_rd 2.580s 0.000us 1 1 100.00
i2c_target_intr_smoke 4.380s 0.000us 1 1 100.00
target_fifo_reset 2 2 100.00
i2c_target_fifo_reset_acq 1.340s 0.000us 1 1 100.00
i2c_target_fifo_reset_tx 1.060s 0.000us 1 1 100.00
target_fifo_full 3 3 100.00
i2c_target_stress_wr 153.340s 0.000us 1 1 100.00
i2c_target_stress_rd 2.580s 0.000us 1 1 100.00
i2c_target_intr_stress_wr 105.390s 0.000us 1 1 100.00
target_timeout 1 1 100.00
i2c_target_timeout 5.010s 0.000us 1 1 100.00
target_clock_stretch 1 1 100.00
i2c_target_stretch 1.750s 0.000us 1 1 100.00
bad_address 1 1 100.00
i2c_target_bad_addr 3.530s 0.000us 1 1 100.00
target_mode_glitch 0 1 0.00
i2c_target_hrst 7.360s 0.000us 0 1 0.00
target_fifo_watermark 2 2 100.00
i2c_target_fifo_watermarks_acq 2.320s 0.000us 1 1 100.00
i2c_target_fifo_watermarks_tx 0.930s 0.000us 1 1 100.00
host_mode_config_perf 2 2 100.00
i2c_host_perf 236.080s 0.000us 1 1 100.00
i2c_host_perf_precise 22.970s 0.000us 1 1 100.00
host_mode_clock_stretching 1 1 100.00
i2c_host_stretch_timeout 7.810s 0.000us 1 1 100.00
target_mode_tx_stretch_ctrl 1 1 100.00
i2c_target_tx_stretch_ctrl 3.090s 0.000us 1 1 100.00
target_mode_nack_generation 3 3 100.00
i2c_target_nack_acqfull 2.130s 0.000us 1 1 100.00
i2c_target_nack_acqfull_addr 1.930s 0.000us 1 1 100.00
i2c_target_nack_txstretch 1.090s 0.000us 1 1 100.00
host_mode_halt_on_nak 1 1 100.00
i2c_host_may_nack 4.820s 0.000us 1 1 100.00
target_mode_smbus_maxlen 1 1 100.00
i2c_target_smbus_maxlen 1.740s 0.000us 1 1 100.00
alert_test 1 1 100.00
i2c_alert_test 0.640s 0.000us 1 1 100.00
intr_test 1 1 100.00
i2c_intr_test 0.770s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
i2c_tl_errors 1.400s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
i2c_tl_errors 1.400s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
i2c_csr_hw_reset 0.720s 0.000us 1 1 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
i2c_csr_aliasing 0.940s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.910s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
i2c_csr_hw_reset 0.720s 0.000us 1 1 100.00
i2c_csr_rw 0.730s 0.000us 1 1 100.00
i2c_csr_aliasing 0.940s 0.000us 1 1 100.00
i2c_same_csr_outstanding 0.910s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
i2c_tl_intg_err 1.260s 0.000us 1 1 100.00
i2c_sec_cm 0.920s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
i2c_tl_intg_err 1.260s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 1 0.00
i2c_host_stress_all_with_rand_reset 8.410s 0.000us 0 1 0.00
target_error_intr 0 1 0.00
i2c_target_unexp_stop 2.510s 0.000us 0 1 0.00
target_stress_all_with_rand_reset 0 1 0.00
i2c_target_stress_all_with_rand_reset 4.880s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
i2c_host_error_intr 6266606806888419724825748777779473307527658228271876410573891577321456602517 86
UVM_ERROR @ 5309563 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 5309563 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_host_stress_all 34982375192292124903609538484711028902716151610541749576419663036771564674544 129
UVM_ERROR @ 68502179643 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 68502179643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
i2c_target_stress_all_with_rand_reset 4644999562907458841690715577923823046390937908653966004422444755018505274468 97
UVM_ERROR @ 512025361 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] Get_next_item called twice without item_done or get in between
UVM_INFO @ 512025361 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
i2c_target_glitch 1068867846217953673798229711728259151982370926532772328986249377925574639736 84
UVM_ERROR @ 675511498 ps: uvm_test_top.env.m_i2c_agent.sequencer [uvm_test_top.env.m_i2c_agent.sequencer] get_next_item/try_next_item called twice without item_done or get in between
UVM_INFO @ 675511498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
i2c_target_unexp_stop 59731986414152586752775161465546496985877975586075049988315885397155744931988 79
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'
UVM_ERROR @ 996286325 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A
UVM_INFO @ 996286325 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
i2c_target_hrst 37192009851795260051083149726572444092473597665553288875744862130515110168338 79
UVM_FATAL @ 10523928331 ps: (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
UVM_INFO @ 10523928331 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
i2c_host_stress_all_with_rand_reset 70603930815158726313376505712611223357002390748966898466618040759440036064021 84
UVM_ERROR @ 208173835 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.i2c_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 208173835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---