Simulation Results: lc_ctrl/volatile_unlock_disabled

 
25/03/2026 17:18:13 DVSim: v1.16.0 sha: 373d38a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.56 %
  • code
  • 83.10 %
  • assert
  • 94.13 %
  • func
  • 91.46 %
  • line
  • 97.12 %
  • branch
  • 93.51 %
  • cond
  • 79.38 %
  • toggle
  • 83.79 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.030s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.180s 0.000us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.930s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.920s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.030s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.930s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.760s 0.000us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 8.400s 0.000us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.000s 0.000us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.130s 0.000us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.290s 0.000us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.780s 0.000us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.290s 0.000us 1 1 100.00
lc_ctrl_prog_failure 3.130s 0.000us 1 1 100.00
lc_ctrl_errors 6.780s 0.000us 1 1 100.00
lc_ctrl_security_escalation 8.140s 0.000us 1 1 100.00
lc_ctrl_jtag_state_failure 37.760s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.590s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 22.130s 0.000us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.300s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.460s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.590s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 22.130s 0.000us 1 1 100.00
lc_ctrl_jtag_access 3.510s 0.000us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 23.060s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.720s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.970s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 8.730s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.750s 0.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.470s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.580s 0.000us 1 1 100.00
lc_ctrl_jtag_alert_test 1.020s 0.000us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.080s 0.000us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.030s 0.000us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 68.360s 0.000us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.770s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.850s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.850s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.180s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.930s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.120s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.180s 0.000us 1 1 100.00
lc_ctrl_csr_rw 0.930s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 0.990s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.120s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.290s 0.000us 1 1 100.00
lc_ctrl_tl_intg_err 1.720s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.720s 0.000us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 8.400s 0.000us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.290s 0.000us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.290s 0.000us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.290s 0.000us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.290s 0.000us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.290s 0.000us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.290s 0.000us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.290s 0.000us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.290s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.290s 0.000us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 8.140s 0.000us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.760s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.460s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.150s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.150s 0.000us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.230s 0.000us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.280s 0.000us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 9.280s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 34.300s 0.000us 1 1 100.00