Simulation Results: rv_timer

 
25/03/2026 17:18:13 DVSim: v1.16.0 sha: 373d38a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.98 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 94.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.600s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.680s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.710s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 1.880s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.880s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.720s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.710s 0.000us 1 1 100.00
rv_timer_csr_aliasing 0.880s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.440s 0.000us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.620s 0.000us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 366.020s 0.000us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 366.020s 0.000us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 4.010s 0.000us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.690s 0.000us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.650s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.530s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.530s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.680s 0.000us 1 1 100.00
rv_timer_csr_rw 0.710s 0.000us 1 1 100.00
rv_timer_csr_aliasing 0.880s 0.000us 1 1 100.00
rv_timer_same_csr_outstanding 0.790s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.680s 0.000us 1 1 100.00
rv_timer_csr_rw 0.710s 0.000us 1 1 100.00
rv_timer_csr_aliasing 0.880s 0.000us 1 1 100.00
rv_timer_same_csr_outstanding 0.790s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_tl_intg_err 1.300s 0.000us 1 1 100.00
rv_timer_sec_cm 0.920s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.300s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.630s 0.000us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.800s 0.000us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 14.130s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 10875569755093888142266046578245507104846472193461988740146069861663384674144 75
UVM_FATAL @ 221545288 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x73cbcd04) == 0x1
UVM_INFO @ 221545288 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 48749383745527936623200548144246546407167939746383044524943930422732146758229 75
UVM_FATAL @ 553160048 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x9b2cd04) == 0x1
UVM_INFO @ 553160048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 64181136100748535467857480408986618353916795631098429419337169684396109612159 75
UVM_ERROR @ 44231435 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 44231435 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---