Simulation Results: adc_ctrl

 
26/03/2026 17:19:52 DVSim: v1.16.0 sha: dbdbe3d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.22 %
  • code
  • 96.38 %
  • assert
  • 95.95 %
  • func
  • 18.34 %
  • line
  • 99.02 %
  • branch
  • 97.71 %
  • cond
  • 93.30 %
  • toggle
  • 100.00 %
  • FSM
  • 91.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.240s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.830s 0.000us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.920s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 70.950s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.740s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 3.070s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.920s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 1.740s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 868.590s 0.000us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 53.790s 0.000us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 74.480s 0.000us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 813.430s 0.000us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 636.360s 0.000us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 247.700s 0.000us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 45.850s 0.000us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 802.190s 0.000us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 10.110s 0.000us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 45.160s 0.000us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 172.090s 0.000us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 279.640s 0.000us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.100s 0.000us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.270s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.820s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.820s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.830s 0.000us 1 1 100.00
adc_ctrl_csr_rw 0.920s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 1.740s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.650s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.830s 0.000us 1 1 100.00
adc_ctrl_csr_rw 0.920s 0.000us 1 1 100.00
adc_ctrl_csr_aliasing 1.740s 0.000us 1 1 100.00
adc_ctrl_same_csr_outstanding 7.650s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 5.210s 0.000us 1 1 100.00
adc_ctrl_tl_intg_err 10.710s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 10.710s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 9.280s 0.000us 1 1 100.00