Simulation Results: chip

 
26/03/2026 17:19:52 DVSim: v1.16.0 sha: dbdbe3d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.42 %
  • code
  • 85.50 %
  • assert
  • 97.37 %
  • func
  • 55.38 %
  • line
  • 94.51 %
  • branch
  • 94.33 %
  • cond
  • 90.31 %
  • toggle
  • 91.19 %
  • FSM
  • 57.14 %
Validation stages
V1
95.65%
V2
85.05%
V2S
50.00%
V3
60.00%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 137.650s 0.000us 1 1 100.00
chip_sw_example_rom 68.180s 0.000us 1 1 100.00
chip_sw_example_manufacturer 164.170s 0.000us 1 1 100.00
chip_sw_example_concurrency 152.640s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 218.600s 0.000us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 342.280s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 849.660s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 3986.620s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
chip_csr_mem_rw_with_rand_reset 44.600s 0.000us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 3986.620s 0.000us 1 1 100.00
chip_csr_rw 342.280s 0.000us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.150s 0.000us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 256.770s 0.000us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 256.770s 0.000us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 256.770s 0.000us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 351.880s 0.000us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 351.880s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx1 385.670s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx2 352.660s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_idx3 387.970s 0.000us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1597.290s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 975.980s 0.000us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 656.960s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 157.030s 0.000us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 157.030s 0.000us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 184.050s 0.000us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 203.400s 0.000us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 156.170s 0.000us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 611.630s 0.000us 1 1 100.00
chip_tap_straps_testunlock0 352.820s 0.000us 1 1 100.00
chip_tap_straps_rma 100.530s 0.000us 1 1 100.00
chip_tap_straps_prod 328.200s 0.000us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 185.640s 0.000us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 841.380s 0.000us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 469.800s 0.000us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 469.800s 0.000us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 615.980s 0.000us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1258.710s 0.000us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 383.420s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 588.130s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3496.870s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 199.170s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 590.450s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 128.250s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1367.670s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 216.960s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 307.630s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 146.820s 0.000us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 184.980s 0.000us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 571.700s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 215.390s 0.000us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 165.510s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 215.390s 0.000us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 167.330s 0.000us 1 1 100.00
chip_sw_aes_smoketest 213.310s 0.000us 1 1 100.00
chip_sw_aon_timer_smoketest 156.990s 0.000us 1 1 100.00
chip_sw_clkmgr_smoketest 161.170s 0.000us 1 1 100.00
chip_sw_csrng_smoketest 148.620s 0.000us 1 1 100.00
chip_sw_entropy_src_smoketest 603.740s 0.000us 1 1 100.00
chip_sw_gpio_smoketest 161.240s 0.000us 1 1 100.00
chip_sw_hmac_smoketest 200.810s 0.000us 1 1 100.00
chip_sw_kmac_smoketest 168.680s 0.000us 1 1 100.00
chip_sw_otbn_smoketest 730.700s 0.000us 1 1 100.00
chip_sw_pwrmgr_smoketest 305.610s 0.000us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 221.470s 0.000us 1 1 100.00
chip_sw_rv_plic_smoketest 143.870s 0.000us 1 1 100.00
chip_sw_rv_timer_smoketest 188.940s 0.000us 1 1 100.00
chip_sw_rstmgr_smoketest 148.650s 0.000us 1 1 100.00
chip_sw_sram_ctrl_smoketest 139.810s 0.000us 1 1 100.00
chip_sw_uart_smoketest 207.440s 0.000us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 140.730s 0.000us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 309.110s 0.000us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7528.440s 0.000us 1 1 100.00
chip_sw_secure_boot 0 1 0.00
rom_e2e_smoke 73.020s 0.000us 0 1 0.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 119.930s 0.000us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 205.700s 0.000us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 200.250s 0.000us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 6671.030s 0.000us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7373.250s 0.000us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 47.090s 0.000us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 47.090s 0.000us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 3986.620s 0.000us 1 1 100.00
chip_same_csr_outstanding 2585.720s 0.000us 1 1 100.00
chip_csr_hw_reset 218.600s 0.000us 1 1 100.00
chip_csr_rw 342.280s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 3986.620s 0.000us 1 1 100.00
chip_same_csr_outstanding 2585.720s 0.000us 1 1 100.00
chip_csr_hw_reset 218.600s 0.000us 1 1 100.00
chip_csr_rw 342.280s 0.000us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 16.950s 0.000us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.030s 0.000us 1 1 100.00
xbar_smoke_large_delays 53.540s 0.000us 1 1 100.00
xbar_smoke_slow_rsp 42.050s 0.000us 1 1 100.00
xbar_random_zero_delays 24.340s 0.000us 1 1 100.00
xbar_random_large_delays 293.170s 0.000us 1 1 100.00
xbar_random_slow_rsp 90.730s 0.000us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 24.930s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 26.680s 0.000us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 20.790s 0.000us 1 1 100.00
xbar_error_and_unmapped_addr 26.680s 0.000us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 15.880s 0.000us 1 1 100.00
xbar_access_same_device_slow_rsp 534.740s 0.000us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 27.900s 0.000us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 137.230s 0.000us 1 1 100.00
xbar_stress_all_with_error 317.690s 0.000us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 737.200s 0.000us 1 1 100.00
xbar_stress_all_with_reset_error 55.760s 0.000us 1 1 100.00
rom_e2e_smoke 0 1 0.00
rom_e2e_smoke 73.020s 0.000us 0 1 0.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2387.220s 0.000us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2312.430s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2004.660s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2541.730s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2596.530s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2477.960s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2483.270s 0.000us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 24.600s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 21.320s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 17.450s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 19.010s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 16.910s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 19.380s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 18.930s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 17.890s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 16.710s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 16.950s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 15.890s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 15.960s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.070s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 15.820s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 16.200s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 15.640s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 16.130s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 16.370s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 16.250s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 16.160s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.780s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 17.150s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 15.940s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 15.850s 0.000us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 18.130s 0.000us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 2011.300s 0.000us 1 1 100.00
rom_e2e_asm_init_dev 2441.420s 0.000us 1 1 100.00
rom_e2e_asm_init_prod 2422.630s 0.000us 1 1 100.00
rom_e2e_asm_init_prod_end 2474.380s 0.000us 1 1 100.00
rom_e2e_asm_init_rma 2419.660s 0.000us 1 1 100.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 4337.040s 0.000us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 4162.540s 0.000us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 4287.060s 0.000us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2409.180s 0.000us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2997.170s 0.000us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2997.170s 0.000us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 148.420s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 199.170s 0.000us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 151.940s 0.000us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 132.600s 0.000us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1510.680s 0.000us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 145.760s 0.000us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 400.800s 0.000us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 387.380s 0.000us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 500.450s 0.000us 1 1 100.00
chip_plic_all_irqs_10 305.820s 0.000us 1 1 100.00
chip_plic_all_irqs_20 331.230s 0.000us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 171.450s 0.000us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1230.400s 0.000us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 292.100s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 172.300s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1075.900s 0.000us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1189.080s 0.000us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 823.480s 0.000us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7054.650s 0.000us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 238.350s 0.000us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 305.610s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 238.350s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 552.450s 0.000us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 552.450s 0.000us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 284.860s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 387.990s 0.000us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 572.920s 0.000us 1 1 100.00
chip_sw_aes_idle 132.600s 0.000us 1 1 100.00
chip_sw_hmac_enc_idle 151.510s 0.000us 1 1 100.00
chip_sw_kmac_idle 108.200s 0.000us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 254.820s 0.000us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 218.310s 0.000us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 252.520s 0.000us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 243.650s 0.000us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 848.580s 0.000us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 412.930s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 419.930s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 386.590s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 362.910s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 355.040s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 382.460s 0.000us 1 1 100.00
chip_sw_ast_clk_outputs 615.980s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 344.330s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 386.590s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 362.910s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 383.420s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 588.130s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3496.870s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en 199.170s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 590.450s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 128.250s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1367.670s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 216.960s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 307.630s 0.000us 1 1 100.00
chip_sw_clkmgr_jitter 146.820s 0.000us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 134.170s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 376.280s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 636.940s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3047.800s 0.000us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 157.110s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 159.580s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 674.950s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 217.600s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 401.050s 0.000us 1 1 100.00
chip_sw_flash_init_reduced_freq 984.570s 0.000us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 9310.110s 0.000us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 615.980s 0.000us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 409.350s 0.000us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 219.590s 0.000us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 387.380s 0.000us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1075.900s 0.000us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 1023.140s 0.000us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 186.020s 0.000us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 457.470s 0.000us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 167.380s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 1688.600s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 127.190s 0.000us 1 1 100.00
chip_sw_edn_entropy_reqs 626.160s 0.000us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 127.190s 0.000us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 1023.140s 0.000us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 171.750s 0.000us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1197.750s 0.000us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 564.960s 0.000us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 588.130s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 348.540s 0.000us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 383.420s 0.000us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3053.430s 0.000us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1197.750s 0.000us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 190.730s 0.000us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1673.500s 0.000us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 168.540s 0.000us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3053.430s 0.000us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 168.540s 0.000us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 168.540s 0.000us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 168.540s 0.000us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 168.540s 0.000us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 387.380s 0.000us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 187.070s 0.000us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 532.230s 0.000us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 472.600s 0.000us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 472.600s 0.000us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 152.310s 0.000us 1 1 100.00
chip_sw_hmac_enc_jitter_en 128.250s 0.000us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 151.510s 0.000us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1549.900s 0.000us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 723.320s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 414.600s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 437.040s 0.000us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 371.950s 0.000us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 297.980s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1673.500s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1367.670s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1441.590s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1510.680s 0.000us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2736.770s 0.000us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 121.970s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac 213.920s 0.000us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 216.960s 0.000us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1673.500s 0.000us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 541.710s 0.000us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 159.650s 0.000us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 640.730s 0.000us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 108.200s 0.000us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 400.800s 0.000us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 611.630s 0.000us 1 1 100.00
chip_tap_straps_rma 100.530s 0.000us 1 1 100.00
chip_tap_straps_prod 328.200s 0.000us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 165.080s 0.000us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 541.710s 0.000us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 541.710s 0.000us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 541.710s 0.000us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1290.220s 0.000us 1 1 100.00
chip_sw_lc_ctrl_broadcast 20 22 90.91
chip_prim_tl_access 187.070s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 286.030s 0.000us 1 1 100.00
chip_sw_flash_ctrl_lc_rw_en 168.540s 0.000us 0 1 0.00
chip_sw_flash_rma_unlocked 3053.430s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 202.670s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 422.290s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 467.540s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 473.540s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 541.710s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1673.500s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 386.890s 0.000us 1 1 100.00
chip_sw_sram_ctrl_execution_main 634.750s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 344.330s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 412.930s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 419.930s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 386.590s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 362.910s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 355.040s 0.000us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 382.460s 0.000us 1 1 100.00
chip_tap_straps_dev 611.630s 0.000us 1 1 100.00
chip_tap_straps_rma 100.530s 0.000us 1 1 100.00
chip_tap_straps_prod 328.200s 0.000us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 172.960s 0.000us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 95.630s 0.000us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 91.210s 0.000us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 95.580s 0.000us 1 1 100.00
chip_lc_test_locked 2 2 100.00
chip_rv_dm_lc_disabled 286.030s 0.000us 1 1 100.00
chip_sw_lc_walkthrough_testunlocks 1603.630s 0.000us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 609.130s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prod 659.560s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_prodend 591.990s 0.000us 1 1 100.00
chip_sw_lc_walkthrough_rma 367.480s 0.000us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1603.630s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 67.030s 0.000us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 56.150s 0.000us 1 1 100.00
rom_volatile_raw_unlock 53.250s 0.000us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3384.900s 0.000us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3496.870s 0.000us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 572.920s 0.000us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 572.920s 0.000us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 572.920s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 301.090s 0.000us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 541.710s 0.000us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1197.750s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 301.090s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1673.500s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 372.990s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 147.420s 0.000us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1197.750s 0.000us 1 1 100.00
chip_sw_otbn_mem_scramble 301.090s 0.000us 1 1 100.00
chip_sw_keymgr_key_derivation 1673.500s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 372.990s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 147.420s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 541.710s 0.000us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 303.610s 0.000us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 165.080s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 187.070s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 202.670s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 422.290s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 467.540s 0.000us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 473.540s 0.000us 0 1 0.00
chip_sw_lc_ctrl_transition 541.710s 0.000us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 187.070s 0.000us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 830.010s 0.000us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 305.770s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1141.950s 0.000us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 234.770s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 349.790s 0.000us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 294.320s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1070.760s 0.000us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 854.330s 0.000us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 552.450s 0.000us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 771.540s 0.000us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 405.020s 0.000us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 305.770s 0.000us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 358.590s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1862.520s 0.000us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 241.400s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 337.430s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 502.960s 0.000us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 701.520s 0.000us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1019.890s 0.000us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1437.070s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 173.900s 0.000us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 387.380s 0.000us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 386.890s 0.000us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 386.890s 0.000us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1019.890s 0.000us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 502.960s 0.000us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 405.020s 0.000us 1 1 100.00
chip_sw_pwrmgr_smoketest 305.610s 0.000us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 267.550s 0.000us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 244.080s 0.000us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 240.150s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1230.400s 0.000us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 160.530s 0.000us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 387.380s 0.000us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1189.080s 0.000us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 500.360s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 482.900s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 152.640s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 147.420s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 244.080s 0.000us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 244.080s 0.000us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 858.270s 0.000us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 790.060s 0.000us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 267.550s 0.000us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 188.070s 0.000us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 379.050s 0.000us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 100.530s 0.000us 1 1 100.00
chip_rv_dm_lc_disabled 1 1 100.00
chip_rv_dm_lc_disabled 286.030s 0.000us 1 1 100.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 500.450s 0.000us 1 1 100.00
chip_plic_all_irqs_10 305.820s 0.000us 1 1 100.00
chip_plic_all_irqs_20 331.230s 0.000us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 139.560s 0.000us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 175.490s 0.000us 1 1 100.00
chip_sw_spi_device_flash_mode 0 1 0.00
rom_e2e_smoke 73.020s 0.000us 0 1 0.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 534.550s 0.000us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 207.620s 0.000us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 220.760s 0.000us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 184.180s 0.000us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 372.990s 0.000us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 307.630s 0.000us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 486.460s 0.000us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 454.850s 0.000us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 634.750s 0.000us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 387.380s 0.000us 1 1 100.00
chip_sw_data_integrity_escalation 469.800s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 701.520s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1102.520s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 139.190s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 204.830s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 364.480s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1102.520s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1102.520s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2365.030s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2365.030s 0.000us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 310.510s 0.000us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2997.170s 0.000us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 139.030s 0.000us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 151.140s 0.000us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 314.110s 0.000us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 326.740s 0.000us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1053.050s 0.000us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 4963.960s 0.000us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1919.170s 0.000us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 132.990s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 145.650s 0.000us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 138.310s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 8632.980s 0.000us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 971.030s 0.000us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 158.830s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 183.290s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 379.770s 0.000us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 66.590s 0.000us 0 1 0.00
rom_e2e_jtag_inject_dev 71.290s 0.000us 0 1 0.00
rom_e2e_jtag_inject_rma 55.350s 0.000us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 8.325s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 228.350s 0.000us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 293.170s 0.000us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 487.730s 0.000us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1320.800s 0.000us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 223.620s 0.000us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 604.020s 0.000us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 168.870s 0.000us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 159.360s 0.000us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 345.910s 0.000us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 328.550s 0.000us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1019.890s 0.000us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 158.830s 0.000us 0 1 0.00
rom_e2e_jtag_debug_dev 183.290s 0.000us 0 1 0.00
rom_e2e_jtag_debug_rma 379.770s 0.000us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 361.040s 0.000us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 387.380s 0.000us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5373.340s 0.000us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5373.340s 0.000us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 178.500s 0.000us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 351.880s 0.000us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 2968.120s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 167.660s 0.000us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 348.220s 0.000us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.100s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 140.430s 0.000us 1 1 100.00
chip_sw_otp_ctrl_descrambling 154.450s 0.000us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 229.990s 0.000us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 10.870s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 180.480s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 30680453305322417627859062251989410500759762667493279642846305255619574882457 217
UVM_ERROR @ 2635.196760 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@40685) { a_addr: 'h10570 a_data: 'hf2abcde4 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h38 a_opcode: 'h4 a_user: 'h1866f d_param: 'h0 d_source: 'h38 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2635.196760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_csr_mem_rw_with_rand_reset 103862283424378638346651572489181342765239026249297375691307921087119057750300 224
UVM_ERROR @ 2602.228966 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@31947) { a_addr: 'h10758 a_data: 'h9281d844 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1e a_opcode: 'h4 a_user: 'h18177 d_param: 'h0 d_source: 'h1e d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2602.228966 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 54407748332929059764156508769684082417896719931301747103587319678662594042500 333
UVM_ERROR @ 3554.569769 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@107059) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h1 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 3554.569769 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
chip_sw_spi_device_pass_through_collision 111383131375407401728686761730278586033609229699318720671344501030880874195158 325
UVM_ERROR @ 3397.186133 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
UVM_INFO @ 3397.186133 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 14694009284051847511327814860616308245422022952373932418960737752562097276542 314
UVM_ERROR @ 2877.284528 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 2877.284528 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 89056468187227605370240942870424469821571104220239725792638468048859298627113 342
UVM_ERROR @ 6984.524535 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 6984.524535 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 86967411931819877324959045204489674793875493016368235651356747444770722685757 316
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2659.787088 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2659.787088 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 103197742331678554448232596227349668607294807918498398410216143746268219871985 312
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3152.661480 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3152.661480 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 109119996632027823541940479049791431179160522936458428421283266552077710525708 282
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 24626144327628495971963660728968528572662438433255634868559388059318594946151 369
UVM_ERROR @ 8249.987810 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 8249.987810 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 62593438981004604640814858022086799116784354560699806658738319728517449222420 369
UVM_ERROR @ 10016.231928 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 10016.231928 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 59877529602496026334288260505865156799574401122272578203258699065591370650885 341
UVM_ERROR @ 6190.928880 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 6190.928880 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 68016468606190231424693774875523071134755987362529603746840181756839394016651 344
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 11979.120000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 11979.120000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 36960846816235050896937280846528386296315354458372872333401275438646328695822 325
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 6958.300000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6958.300000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 86823009013719117627208574718203963367206250982424601582120727809568317027020 432
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 28420.218500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 28420.218500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 79028805936994287872928790375508465521214011815150751449549146470114379680490 332
UVM_ERROR @ 34992.168500 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 34992.168500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *!
chip_sw_alert_test 72885281829255100181930209352707321425872932202554360403972473451654520523738 307
UVM_ERROR @ 2848.881616 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 43!
UVM_INFO @ 2848.881616 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 105274075091169177931761277860457059892490288937855160028464649640123050344242 313
UVM_ERROR @ 3162.724418 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 3162.724418 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 93756770313914862269768446549564267731408325174076643394652873175468478170357 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 80735769287497664076041080860151221505357360464547562482481431118032197815104 348
UVM_ERROR @ 3637.823774 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 3637.823774 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 82690758748168364948434128678869687656103502592246167192412785200161495681297 None
---- STDERR ----
Another command (pid=1921286) is running. Waiting for it to complete on the server (server_pid=728241)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 89148390937548025742639467197477452284074819856671628309753288031429773078125 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 112416620471299934184457839740449969549765724285822620988311943368182864859848 332
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 94019934066315505969063096751534642858821655722203177885458272638108688442980 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 108908611772276114146501368959586514281522157233681179537299947890161739100800 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_rma 84158636478330742883140312157714641609244009470765949026052492115963556180608 352
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 107795272275304501015796608928578928785423801426989712756407352620634341877227 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 69571768729115784840921424550150420544866927832553743751389646327105660437273 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 43669848787359550495043704329373453784233112791422548090695665783101212815084 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 3241188275817505773464064608140465859246854438456158162547286075803957059355 327
UVM_FATAL @ 2470.274000 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2470.274000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 110281294247224899262205428601005752627489109386949865434521078648219791175231 312
UVM_ERROR @ 3731.756000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3731.756000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 30205652374784753122579267237807661206689737194417500359883572069790729676400 318
UVM_ERROR @ 3414.240000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH3 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3414.240000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 62548313383173779254613455145683635889107191624770841440310871359578542812376 327
UVM_ERROR @ 12870.506433 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 12870.506433 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(reset_cause == HwReq)'
rom_e2e_smoke 21815964243012048952746374564919904644788004394662204202008446715044317830698 317
Offending '(reset_cause == HwReq)'
UVM_ERROR @ 2681.739630 us: (pwrmgr_rstreqs_sva_if.sv:98) [ASSERT FAILED] SwResetSetCause_A
UVM_INFO @ 2681.739630 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 21693809150626982917919765990211807827209440137024691818556527636257322672873 351
UVM_FATAL @ 10.240001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 100906890732041312813227183030238267810394869353359677491284546193910858073582 353
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 30275014041358954761649383660467542569721161500181685041293399519005915449682 356
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 50451695095602448557975292085338090381750164506760642985263635380621279481156 349
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 20428622249446051728091224502853968428456615524629049453817222039478289478630 350
UVM_FATAL @ 10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 75466549039755931145616565006963679735201251968290243944589634259099626301368 348
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 43233336401706099940447514271974118160629295634642415916710438035785326956275 348
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 230811634021289487017701395349699879993040544104723934249964571368808775659 346
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 87465425043656000518716781773102781788986752182708492211446843681217026602871 347
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 84448368311009404533372769094950991012775560939559420327936195444132722079205 349
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 47907094764272426932318048231533739008743042210748374799153453891664122338697 359
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 115727401356590429705744896211330760743376435341603466104478105605047094038265 359
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 110533016007176038387520090327186026657457220638379097993517889035917779599062 359
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 67009440467535267583586309647403829214655727705770532331343467531867199392969 325
UVM_FATAL @ 10.180001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 42851290563702185720146817578304629962004787238747497198011724508530624492195 325
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 73477730642782609506314096533990955680353657754317449696361080092877144247892 325
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 35162733805576362403884455051331770942215573232158962436245139474332351851674 362
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 7224930739126683530678639720748358302746265344799751696683609653578067156397 323
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 62897649992968838729919618565434003061455417365622264540073072821624004878516 359
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 11819417303078474865300544485509237172357710708975057972515885439227361791045 324
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 3884959854965365873333958735751195574029530157207840387784075161185196617377 323
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 30512336199753618519740267398826385574316672708222511427395004086797725631368 325
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 103571503889278750375528579869955433956696743020120302954274233424531163683348 323
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 73690546830332967014369997034278192043781986079256090768732318935185257680055 325
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 21573215154028187769441150748731650468336360187062297054654327805504691827054 322
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 66928971883777143167439523816182937893505931941524121798519082820291251399610 332
Offending '$stable(key_data_i)'
UVM_ERROR @ 5049.715356 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 5049.715356 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---