Simulation Results: clkmgr

 
26/03/2026 17:19:52 DVSim: v1.16.0 sha: dbdbe3d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.01 %
  • code
  • 98.08 %
  • assert
  • 95.20 %
  • func
  • 85.76 %
  • line
  • 98.97 %
  • branch
  • 98.62 %
  • cond
  • 93.61 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
85.71%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 1.060s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.900s 0.000us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.250s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.260s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.200s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.910s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.250s 0.000us 1 1 100.00
clkmgr_csr_aliasing 1.200s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.860s 0.000us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.820s 0.000us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.780s 0.000us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.710s 0.000us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 1.060s 0.000us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.910s 0.000us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.120s 0.000us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.910s 0.000us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 35.040s 0.000us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 1.040s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.930s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.930s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.900s 0.000us 1 1 100.00
clkmgr_csr_rw 1.250s 0.000us 1 1 100.00
clkmgr_csr_aliasing 1.200s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 1.080s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.900s 0.000us 1 1 100.00
clkmgr_csr_rw 1.250s 0.000us 1 1 100.00
clkmgr_csr_aliasing 1.200s 0.000us 1 1 100.00
clkmgr_same_csr_outstanding 1.080s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_tl_intg_err 1.500s 0.000us 1 1 100.00
clkmgr_sec_cm 0.840s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 2.770s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 2.770s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 2.770s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 2.770s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.980s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.500s 0.000us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.910s 0.000us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.120s 0.000us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 2.770s 0.000us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 1.020s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.860s 0.000us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 1.080s 0.000us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.940s 0.000us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.720s 0.000us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.250s 0.000us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.840s 0.000us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.250s 0.000us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.250s 0.000us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.840s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.380s 0.000us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 7.120s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 37378328618136999290687875955585727186166993590019548425039513604283656347754 91
UVM_ERROR @ 26792955 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 26792955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---