Simulation Results: flash_ctrl

 
26/03/2026 17:19:52 DVSim: v1.16.0 sha: dbdbe3d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.36 %
  • code
  • 93.98 %
  • assert
  • 96.76 %
  • func
  • 95.33 %
  • line
  • 95.95 %
  • branch
  • 96.99 %
  • cond
  • 93.76 %
  • toggle
  • 97.51 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.45%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 29.560s 0.000us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 8.680s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 11.820s 0.000us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.430s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 21.860s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 20.500s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 6.370s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.430s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 20.500s 0.000us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.870s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.050s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 10.190s 0.000us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 24.560s 0.000us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1243.000s 0.000us 1 1 100.00
flash_ctrl_hw_rma_reset 560.220s 0.000us 1 1 100.00
flash_ctrl_lcmgr_intg 5.300s 0.000us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1180.970s 0.000us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 233.990s 0.000us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.530s 0.000us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2558.980s 0.000us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 48.870s 0.000us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.090s 0.000us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.510s 0.000us 1 1 100.00
flash_ctrl_re_evict 16.520s 0.000us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 164.880s 0.000us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 164.880s 0.000us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 127.980s 0.000us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 13.170s 0.000us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 49.870s 0.000us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 282.340s 0.000us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 292.010s 0.000us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 700.350s 0.000us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 5.280s 0.000us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 104.660s 0.000us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.890s 0.000us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 6.960s 0.000us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 401.660s 0.000us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 49.350s 0.000us 1 1 100.00
flash_ctrl_otp_reset 38.540s 0.000us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1243.000s 0.000us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 122.250s 0.000us 1 1 100.00
flash_ctrl_intr_wr 56.590s 0.000us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 76.910s 0.000us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 126.110s 0.000us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 50.810s 0.000us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.590s 0.000us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.110s 0.000us 1 1 100.00
flash_ctrl_ro_derr 97.760s 0.000us 1 1 100.00
flash_ctrl_rw_derr 156.040s 0.000us 1 1 100.00
flash_ctrl_derr_detect 90.860s 0.000us 1 1 100.00
flash_ctrl_integrity 369.900s 0.000us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 9.370s 0.000us 1 1 100.00
flash_ctrl_ro_serr 82.940s 0.000us 1 1 100.00
flash_ctrl_rw_serr 113.810s 0.000us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 41.030s 0.000us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 40.810s 0.000us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 101.850s 0.000us 1 1 100.00
flash_ctrl_write_word_sweep 7.870s 0.000us 1 1 100.00
flash_ctrl_read_word_sweep 6.850s 0.000us 1 1 100.00
flash_ctrl_ro 81.870s 0.000us 1 1 100.00
flash_ctrl_rw 320.920s 0.000us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.560s 0.000us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 619.360s 0.000us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 64.020s 0.000us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.520s 0.000us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.480s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 10.120s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 10.120s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 11.820s 0.000us 1 1 100.00
flash_ctrl_csr_rw 8.430s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 20.500s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.500s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 11.820s 0.000us 1 1 100.00
flash_ctrl_csr_rw 8.430s 0.000us 1 1 100.00
flash_ctrl_csr_aliasing 20.500s 0.000us 1 1 100.00
flash_ctrl_same_csr_outstanding 10.500s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 32.720s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 32.720s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 32.720s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 32.720s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 17.120s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_tl_intg_err 266.280s 0.000us 1 1 100.00
flash_ctrl_sec_cm 1552.840s 0.000us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 266.280s 0.000us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 266.280s 0.000us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 12.470s 0.000us 1 1 100.00
flash_ctrl_wr_intg 9.390s 0.000us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 29.560s 0.000us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 38.540s 0.000us 1 1 100.00
flash_ctrl_disable 9.890s 0.000us 1 1 100.00
flash_ctrl_sec_info_access 43.530s 0.000us 1 1 100.00
flash_ctrl_connect 6.960s 0.000us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.490s 0.000us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.430s 0.000us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 32.720s 0.000us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.430s 0.000us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 32.720s 0.000us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.430s 0.000us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 32.720s 0.000us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.890s 0.000us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 12.470s 0.000us 1 1 100.00
flash_ctrl_access_after_disable 5.430s 0.000us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.010s 0.000us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.890s 0.000us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 13.170s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 320.920s 0.000us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 113.810s 0.000us 1 1 100.00
flash_ctrl_rw_derr 156.040s 0.000us 1 1 100.00
flash_ctrl_integrity 369.900s 0.000us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1243.000s 0.000us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1552.840s 0.000us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1552.840s 0.000us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1552.840s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1552.840s 0.000us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.570s 0.000us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 0 1 0.00
flash_ctrl_phy_host_grant_err 5.600s 0.000us 0 1 0.00
sec_cm_phy_ack_ctrl_consistency 0 1 0.00
flash_ctrl_phy_ack_consistency 5.650s 0.000us 0 1 0.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1552.840s 0.000us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1552.840s 0.000us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1552.840s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 19.030s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 299.660s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
flash_ctrl_phy_host_grant_err 30821484363242199403667537368884534291977961375638015099250048683341746533513 125
Offending '(!$isunknown((alert_tx.alert_p ^ alert_tx.alert_n)))'
UVM_ERROR @ 5971.2 ns: (alert_esc_if.sv:202) [ASSERT FAILED] AlertKnown_A
UVM_INFO @ 5971.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (*) != exp (*)
flash_ctrl_phy_ack_consistency 39694038508618020372967902173492847755920679571511969457982135705153056484475 116
UVM_ERROR @ 47545.4 ns: (cip_tl_seq_item.sv:227) [req] d_user.data_intg act (0x2a) != exp (0x50)
UVM_INFO @ 47545.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---