Simulation Results: kmac/masked

 
26/03/2026 17:19:52 DVSim: v1.16.0 sha: dbdbe3d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 94.55 %
  • code
  • 90.67 %
  • assert
  • 97.98 %
  • func
  • 94.99 %
  • line
  • 99.00 %
  • branch
  • 96.30 %
  • cond
  • 92.37 %
  • toggle
  • 99.48 %
  • FSM
  • 66.20 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 34.710s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.020s 0.000us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.950s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 7.130s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.610s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.730s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.950s 0.000us 1 1 100.00
kmac_csr_aliasing 3.610s 0.000us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.680s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.320s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2075.690s 0.000us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 236.730s 0.000us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 26.890s 0.000us 1 1 100.00
kmac_test_vectors_sha3_256 25.450s 0.000us 1 1 100.00
kmac_test_vectors_sha3_384 20.830s 0.000us 1 1 100.00
kmac_test_vectors_sha3_512 1110.660s 0.000us 1 1 100.00
kmac_test_vectors_shake_128 198.670s 0.000us 1 1 100.00
kmac_test_vectors_shake_256 269.930s 0.000us 1 1 100.00
kmac_test_vectors_kmac 1.900s 0.000us 1 1 100.00
kmac_test_vectors_kmac_xof 2.260s 0.000us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 137.730s 0.000us 1 1 100.00
app 1 1 100.00
kmac_app 205.040s 0.000us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 92.490s 0.000us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 257.320s 0.000us 1 1 100.00
error 1 1 100.00
kmac_error 234.650s 0.000us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 9.160s 0.000us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 5.390s 0.000us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 0.910s 0.000us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 23.940s 0.000us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 25.300s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.250s 0.000us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 1841.760s 0.000us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.730s 0.000us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.860s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.920s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.920s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.020s 0.000us 1 1 100.00
kmac_csr_rw 0.950s 0.000us 1 1 100.00
kmac_csr_aliasing 3.610s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.920s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.020s 0.000us 1 1 100.00
kmac_csr_rw 0.950s 0.000us 1 1 100.00
kmac_csr_aliasing 3.610s 0.000us 1 1 100.00
kmac_same_csr_outstanding 1.920s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.700s 0.000us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.700s 0.000us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.700s 0.000us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.700s 0.000us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 3.570s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_tl_intg_err 2.250s 0.000us 1 1 100.00
kmac_sec_cm 33.400s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.250s 0.000us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.250s 0.000us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 34.710s 0.000us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 137.730s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.700s 0.000us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 33.400s 0.000us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 33.400s 0.000us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 33.400s 0.000us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 34.710s 0.000us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.250s 0.000us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 33.400s 0.000us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 83.250s 0.000us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 34.710s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 185.840s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:847) [kmac_common_vseq] Check failed data & ~ro_mask == * (* [*] vs * [*])
kmac_stress_all_with_rand_reset 62434599157343402180735374410946240914446878561739015797280295172995642545476 443
UVM_ERROR @ 7830677983 ps: (cip_base_vseq.sv:847) [uvm_test_top.env.virtual_sequencer.kmac_common_vseq] Check failed data & ~ro_mask == 0 (4 [0x4] vs 0 [0x0])
UVM_INFO @ 7830677983 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---