Simulation Results: lc_ctrl/volatile_unlock_enabled

 
26/03/2026 17:19:52 DVSim: v1.16.0 sha: dbdbe3d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 89.70 %
  • code
  • 82.63 %
  • assert
  • 94.13 %
  • func
  • 92.35 %
  • line
  • 97.10 %
  • branch
  • 93.47 %
  • cond
  • 79.01 %
  • toggle
  • 82.82 %
  • FSM
  • 60.75 %
Validation stages
V1
100.00%
V2
97.50%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.980s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.340s 0.000us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.070s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.390s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.050s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.070s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 3.430s 0.000us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.460s 0.000us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.790s 0.000us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.350s 0.000us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.370s 0.000us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.760s 0.000us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.370s 0.000us 1 1 100.00
lc_ctrl_prog_failure 1.350s 0.000us 1 1 100.00
lc_ctrl_errors 6.760s 0.000us 1 1 100.00
lc_ctrl_security_escalation 4.320s 0.000us 1 1 100.00
lc_ctrl_jtag_state_failure 30.250s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 10.910s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 35.080s 0.000us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.280s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.300s 0.000us 1 1 100.00
lc_ctrl_jtag_prog_failure 10.910s 0.000us 1 1 100.00
lc_ctrl_jtag_errors 35.080s 0.000us 1 1 100.00
lc_ctrl_jtag_access 2.830s 0.000us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 17.130s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.910s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.980s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 11.520s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 4.110s 0.000us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.270s 0.000us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.060s 0.000us 1 1 100.00
lc_ctrl_jtag_alert_test 1.380s 0.000us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.700s 0.000us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.920s 0.000us 1 1 100.00
stress_all 0 1 0.00
lc_ctrl_stress_all 40.840s 0.000us 0 1 0.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.900s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.510s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.510s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.340s 0.000us 1 1 100.00
lc_ctrl_csr_rw 1.070s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.310s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.340s 0.000us 1 1 100.00
lc_ctrl_csr_rw 1.070s 0.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.520s 0.000us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.310s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.070s 0.000us 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 3.000s 0.000us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.460s 0.000us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.370s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.070s 0.000us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.370s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.070s 0.000us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.370s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.070s 0.000us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.370s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.070s 0.000us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.370s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.070s 0.000us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.370s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.070s 0.000us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.370s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.070s 0.000us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.370s 0.000us 1 1 100.00
lc_ctrl_sec_cm 6.070s 0.000us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 4.320s 0.000us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 3.430s 0.000us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.300s 0.000us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.700s 0.000us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.700s 0.000us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 10.090s 0.000us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.840s 0.000us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.840s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 37.830s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_prog_error did not trigger max_delay:*
lc_ctrl_stress_all 64982999584984022309921102193438210816475431394926396894519572080820275772155 9588
UVM_ERROR @ 3622264139 ps: (cip_base_scoreboard.sv:353) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_prog_error did not trigger max_delay:2000
UVM_INFO @ 3622264139 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 31814486443078933922400433692601774103823099567506422413028808980984393414729 1456
UVM_ERROR @ 7526704491 ps: (cip_base_vseq.sv:1236) [uvm_test_top.env.virtual_sequencer.lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7526704491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---