Simulation Results: otbn

 
26/03/2026 17:19:52 DVSim: v1.16.0 sha: dbdbe3d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.15 %
  • code
  • 95.29 %
  • assert
  • 89.70 %
  • func
  • 97.46 %
  • block
  • 99.37 %
  • line
  • 99.56 %
  • branch
  • 92.15 %
  • toggle
  • 92.00 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
95.16%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 0.000us 1 1 100.00
single_binary 1 1 100.00
otbn_single 9.000s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 4.000s 0.000us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 4.000s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 94.000s 0.000us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 32.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 37.000s 0.000us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 42.000s 0.000us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 34.000s 0.000us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 82.000s 0.000us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 10.000s 0.000us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 0.000us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 0.000us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 3.000s 0.000us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 3.000s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 4.000s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 4.000s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 4.000s 0.000us 1 1 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
otbn_same_csr_outstanding 3.000s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 4.000s 0.000us 1 1 100.00
otbn_csr_rw 3.000s 0.000us 1 1 100.00
otbn_csr_aliasing 3.000s 0.000us 1 1 100.00
otbn_same_csr_outstanding 3.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 10.000s 0.000us 1 1 100.00
otbn_dmem_err 8.000s 0.000us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 8.000s 0.000us 1 1 100.00
otbn_controller_ispr_rdata_err 8.000s 0.000us 1 1 100.00
otbn_mac_bignum_acc_err 9.000s 0.000us 1 1 100.00
otbn_urnd_err 7.000s 0.000us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 9.000s 0.000us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 7.000s 0.000us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 0.000us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
otbn_tl_intg_err 9.000s 0.000us 1 1 100.00
passthru_mem_tl_intg_err 0 1 0.00
otbn_passthru_mem_tl_intg_err 14.000s 0.000us 0 1 0.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 0.000us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 8.000s 0.000us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 10.000s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 9.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 10.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 0.000us 1 1 100.00
otbn_dmem_err 8.000s 0.000us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 9.000s 0.000us 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 9.000s 0.000us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 0.000us 1 1 100.00
otbn_dmem_err 8.000s 0.000us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 9.000s 0.000us 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 10.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 10.000s 0.000us 1 1 100.00
otbn_dmem_err 8.000s 0.000us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 0.000us 1 1 100.00
otbn_illegal_mem_acc 9.000s 0.000us 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 9.000s 0.000us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 0.000us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 0.000us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 59.000s 0.000us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 59.000s 0.000us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 7.000s 0.000us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 13.000s 0.000us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 0.000us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 0.000us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 9.000s 0.000us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 0.000us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 9.000s 0.000us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 9.000s 0.000us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 34.000s 0.000us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 9.000s 0.000us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 9.000s 0.000us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 11.000s 0.000us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 9.000s 0.000us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 353.000s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 149.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 6.000s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 46382913326993547173575439374793783407174442309869407373334559034683894316816 166
UVM_ERROR @ 1071186096 ps: (cip_base_vseq.sv:1237) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 1071186096 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed
otbn_stack_addr_integ_chk 19105165452926820603411722486729491106890001744524218391429288471966049336597 117
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_0.1/otbn_insn_cnt_if.sv,21): (time 5570206 PS) Assertion tb.insn_cnt_if.InsnCntMatches_A has failed
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_model_agent_0.1/otbn_model_if.sv,152): (time 5570206 PS) Assertion tb.model_if.NoModelErrs has failed
UVM_ERROR @ 5570206 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 5570206 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
otbn_passthru_mem_tl_intg_err 83058186372949491451317918482970347591277483475367599362439406047702577450469 116
UVM_FATAL @ 58811367 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
UVM_INFO @ 58811367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---