Simulation Results

Simulation Results: otp_ctrl

26/03/2026 17:19:52 DVSim: v1.16.0 sha: dbdbe3d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
78.35 %

code
75.65 %

assert
91.94 %

func
67.47 %

line
88.40 %

branch
81.52 %

cond
89.03 %

toggle
76.58 %

FSM
42.71 %

Validation stages

V1		90.91%
V2		88.00%
V2S		50.00%
V3		50.00%

10/11 passed

90.91 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
wake_up				1	1	100.00
	otp_ctrl_wake_up	1.830s	0.000us	1	1	100.00
smoke				1	1	100.00
	otp_ctrl_smoke	4.160s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	otp_ctrl_csr_hw_reset	1.720s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	otp_ctrl_csr_rw	1.410s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	otp_ctrl_csr_bit_bash	7.100s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	otp_ctrl_csr_aliasing	4.930s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	otp_ctrl_csr_mem_rw_with_rand_reset	1.400s	0.000us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	otp_ctrl_csr_rw	1.410s	0.000us	1	1	100.00
	otp_ctrl_csr_aliasing	4.930s	0.000us	1	1	100.00
mem_walk				1	1	100.00
	otp_ctrl_mem_walk	2.270s	0.000us	1	1	100.00
mem_partial_access				1	1	100.00
	otp_ctrl_mem_partial_access	1.630s	0.000us	1	1	100.00

22/25 passed

88.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
dai_access_partition_walk				1	1	100.00
	otp_ctrl_partition_walk	11.800s	0.000us	1	1	100.00
init_fail				1	1	100.00
	otp_ctrl_init_fail	3.850s	0.000us	1	1	100.00
partition_check				0	2	0.00
	otp_ctrl_background_chks	23.910s	0.000us	0	1	0.00
	otp_ctrl_check_fail	1.350s	0.000us	0	1	0.00
regwen_during_otp_init				1	1	100.00
	otp_ctrl_regwen	3.010s	0.000us	1	1	100.00
partition_lock				1	1	100.00
	otp_ctrl_dai_lock	12.260s	0.000us	1	1	100.00
interface_key_check				1	1	100.00
	otp_ctrl_parallel_key_req	6.810s	0.000us	1	1	100.00
lc_interactions				2	2	100.00
	otp_ctrl_parallel_lc_req	5.440s	0.000us	1	1	100.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
otp_dai_errors				1	1	100.00
	otp_ctrl_dai_errs	4.820s	0.000us	1	1	100.00
otp_macro_errors				0	1	0.00
	otp_ctrl_macro_errs	5.810s	0.000us	0	1	0.00
test_access				1	1	100.00
	otp_ctrl_test_access	11.750s	0.000us	1	1	100.00
stress_all				1	1	100.00
	otp_ctrl_stress_all	33.680s	0.000us	1	1	100.00
intr_test				1	1	100.00
	otp_ctrl_intr_test	1.860s	0.000us	1	1	100.00
alert_test				1	1	100.00
	otp_ctrl_alert_test	1.390s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	otp_ctrl_tl_errors	2.430s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	otp_ctrl_tl_errors	2.430s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	otp_ctrl_csr_hw_reset	1.720s	0.000us	1	1	100.00
	otp_ctrl_csr_rw	1.410s	0.000us	1	1	100.00
	otp_ctrl_csr_aliasing	4.930s	0.000us	1	1	100.00
	otp_ctrl_same_csr_outstanding	1.860s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	otp_ctrl_csr_hw_reset	1.720s	0.000us	1	1	100.00
	otp_ctrl_csr_rw	1.410s	0.000us	1	1	100.00
	otp_ctrl_csr_aliasing	4.930s	0.000us	1	1	100.00
	otp_ctrl_same_csr_outstanding	1.860s	0.000us	1	1	100.00

V2S

28/56 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
sec_cm_additional_check				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
tl_intg_err				1	2	50.00
	otp_ctrl_tl_intg_err	19.560s	0.000us	1	1	100.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
prim_count_check				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
prim_fsm_check				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_bus_integrity				1	1	100.00
	otp_ctrl_tl_intg_err	19.560s	0.000us	1	1	100.00
sec_cm_secret_mem_scramble				1	1	100.00
	otp_ctrl_smoke	4.160s	0.000us	1	1	100.00
sec_cm_part_mem_digest				1	1	100.00
	otp_ctrl_smoke	4.160s	0.000us	1	1	100.00
sec_cm_dai_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_kdi_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_lci_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_part_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_scrmbl_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_timer_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_dai_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_kdi_seed_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_kdi_entropy_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_lci_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_part_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_scrmbl_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_timer_integ_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_timer_cnsty_ctr_redun				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_timer_lfsr_redun				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_dai_fsm_local_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_lci_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
sec_cm_kdi_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
sec_cm_part_fsm_local_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
	otp_ctrl_macro_errs	5.810s	0.000us	0	1	0.00
sec_cm_scrmbl_fsm_local_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
sec_cm_timer_fsm_local_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_dai_fsm_global_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_lci_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
sec_cm_kdi_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
sec_cm_part_fsm_global_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
	otp_ctrl_macro_errs	5.810s	0.000us	0	1	0.00
sec_cm_scrmbl_fsm_global_esc				1	1	100.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
sec_cm_timer_fsm_global_esc				1	2	50.00
	otp_ctrl_parallel_lc_esc	6.630s	0.000us	1	1	100.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_part_data_reg_integrity				1	1	100.00
	otp_ctrl_init_fail	3.850s	0.000us	1	1	100.00
sec_cm_part_data_reg_bkgn_chk				0	1	0.00
	otp_ctrl_check_fail	1.350s	0.000us	0	1	0.00
sec_cm_part_mem_regren				1	1	100.00
	otp_ctrl_dai_lock	12.260s	0.000us	1	1	100.00
sec_cm_part_mem_sw_unreadable				1	1	100.00
	otp_ctrl_dai_lock	12.260s	0.000us	1	1	100.00
sec_cm_part_mem_sw_unwritable				1	1	100.00
	otp_ctrl_dai_lock	12.260s	0.000us	1	1	100.00
sec_cm_lc_part_mem_sw_noaccess				1	1	100.00
	otp_ctrl_dai_lock	12.260s	0.000us	1	1	100.00
sec_cm_access_ctrl_mubi				1	1	100.00
	otp_ctrl_dai_lock	12.260s	0.000us	1	1	100.00
sec_cm_token_valid_ctrl_mubi				1	1	100.00
	otp_ctrl_smoke	4.160s	0.000us	1	1	100.00
sec_cm_lc_ctrl_intersig_mubi				1	1	100.00
	otp_ctrl_dai_lock	12.260s	0.000us	1	1	100.00
sec_cm_test_bus_lc_gated				1	1	100.00
	otp_ctrl_smoke	4.160s	0.000us	1	1	100.00
sec_cm_test_tl_lc_gate_fsm_sparse				0	1	0.00
	otp_ctrl_sec_cm	42.660s	0.000us	0	1	0.00
sec_cm_direct_access_config_regwen				1	1	100.00
	otp_ctrl_regwen	3.010s	0.000us	1	1	100.00
sec_cm_check_trigger_config_regwen				1	1	100.00
	otp_ctrl_smoke	4.160s	0.000us	1	1	100.00
sec_cm_check_config_regwen				1	1	100.00
	otp_ctrl_smoke	4.160s	0.000us	1	1	100.00
sec_cm_macro_mem_integrity				0	1	0.00
	otp_ctrl_macro_errs	5.810s	0.000us	0	1	0.00

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
otp_ctrl_low_freq_read				1	1	100.00
	otp_ctrl_low_freq_read	8.040s	0.000us	1	1	100.00
stress_all_with_rand_reset				0	1	0.00
	otp_ctrl_stress_all_with_rand_reset	1.180s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [] vs []) d_data mismatch when d_error =
	otp_ctrl_csr_mem_rw_with_rand_reset	86879015295058463530287233837430614108175765681123688543478574199827657599752	92	UVM_ERROR @ 52686756 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1 UVM_INFO @ 52686756 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_stress_all_with_rand_reset	33613869965927378064989928355731930691019984392123836523026923847216460598354	93	UVM_ERROR @ 29623171 ps: (cip_base_scoreboard.sv:632) [uvm_test_top.env.scoreboard] Check failed item.d_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) d_data mismatch when d_error = 1 UVM_INFO @ 29623171 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [] vs [*]) fatal error fatal_check_error does not trigger!
	otp_ctrl_background_chks	25239156849137510712759571921647169938616447371580477943877333091457186201066	17344	UVM_ERROR @ 21299541870 ps: (cip_base_vseq.sv:1315) [uvm_test_top.env.virtual_sequencer.otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_check_error does not trigger! UVM_INFO @ 21299541870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [] vs []) reg name: otp_ctrl_core_reg_block.direct_access_rdata_
	otp_ctrl_check_fail	44553049896792274356349057412373064395483163565543502365999244359955066572313	167	UVM_ERROR @ 34056034 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1351205349 [0x5089c1e5] vs 1351205365 [0x5089c1f5]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0 UVM_INFO @ 34056034 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	otp_ctrl_macro_errs	226349710789704654226914003178101517789301225834748309617119169729834580852	6153	UVM_ERROR @ 844788121 ps: (otp_ctrl_scoreboard.sv:1202) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 8 [0x8]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_0 UVM_INFO @ 844788121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [otp_ctrl_common_vseq] expect alert:fatal_check_error to fire
	otp_ctrl_sec_cm	105097650582963696804938950417807876952102379582994871515287821636606876818952	615	UVM_ERROR @ 34912301373 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.otp_ctrl_common_vseq] expect alert:fatal_check_error to fire UVM_INFO @ 34912301373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---