Simulation Results: rv_timer

 
26/03/2026 17:19:52 DVSim: v1.16.0 sha: dbdbe3d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.76 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 96.47 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
94.12%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.140s 0.000us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.560s 0.000us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.550s 0.000us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.320s 0.000us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.630s 0.000us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.630s 0.000us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.550s 0.000us 1 1 100.00
rv_timer_csr_aliasing 0.630s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.150s 0.000us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.190s 0.000us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 0.670s 0.000us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 0.670s 0.000us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 0.730s 0.000us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.550s 0.000us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.550s 0.000us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.740s 0.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.740s 0.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 0.000us 1 1 100.00
rv_timer_csr_rw 0.550s 0.000us 1 1 100.00
rv_timer_csr_aliasing 0.630s 0.000us 1 1 100.00
rv_timer_same_csr_outstanding 0.700s 0.000us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.560s 0.000us 1 1 100.00
rv_timer_csr_rw 0.550s 0.000us 1 1 100.00
rv_timer_csr_aliasing 0.630s 0.000us 1 1 100.00
rv_timer_same_csr_outstanding 0.700s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.680s 0.000us 1 1 100.00
rv_timer_tl_intg_err 0.910s 0.000us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.910s 0.000us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.640s 0.000us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 0.530s 0.000us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 20.180s 0.000us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 18028715875926667551377592584158179495591863021524639162711857448221215590108 75
UVM_ERROR @ 85968424 ps: (rv_timer_scoreboard.sv:231) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
UVM_INFO @ 85968424 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_random_reset 75056015496125568054919161079960036346199951262070841732076713593905960533609 77
UVM_FATAL @ 1300754829 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0xc17a0d04) == 0x1
UVM_INFO @ 1300754829 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---