Simulation Results

Simulation Results: uart

26/03/2026 17:19:52 DVSim: v1.16.0 sha: dbdbe3d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
81.88 %

code
95.06 %

assert
97.12 %

func
53.45 %

line
98.86 %

branch
96.50 %

cond
93.35 %

toggle
91.55 %

Validation stages

V1		100.00%
V2		97.06%
V2S		100.00%
V3		0.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	uart_smoke	0.960s	0.000us	1	1	100.00
csr_hw_reset				1	1	100.00
	uart_csr_hw_reset	0.620s	0.000us	1	1	100.00
csr_rw				1	1	100.00
	uart_csr_rw	0.650s	0.000us	1	1	100.00
csr_bit_bash				1	1	100.00
	uart_csr_bit_bash	1.770s	0.000us	1	1	100.00
csr_aliasing				1	1	100.00
	uart_csr_aliasing	0.580s	0.000us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	uart_csr_mem_rw_with_rand_reset	0.980s	0.000us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	uart_csr_rw	0.650s	0.000us	1	1	100.00
	uart_csr_aliasing	0.580s	0.000us	1	1	100.00

33/34 passed

97.06 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
base_random_seq				1	1	100.00
	uart_tx_rx	64.490s	0.000us	1	1	100.00
parity				2	2	100.00
	uart_smoke	0.960s	0.000us	1	1	100.00
	uart_tx_rx	64.490s	0.000us	1	1	100.00
parity_error				2	2	100.00
	uart_intr	45.900s	0.000us	1	1	100.00
	uart_rx_parity_err	6.880s	0.000us	1	1	100.00
watermark				2	2	100.00
	uart_tx_rx	64.490s	0.000us	1	1	100.00
	uart_intr	45.900s	0.000us	1	1	100.00
fifo_full				1	1	100.00
	uart_fifo_full	41.180s	0.000us	1	1	100.00
fifo_overflow				1	1	100.00
	uart_fifo_overflow	35.130s	0.000us	1	1	100.00
fifo_reset				1	1	100.00
	uart_fifo_reset	21.190s	0.000us	1	1	100.00
rx_frame_err				1	1	100.00
	uart_intr	45.900s	0.000us	1	1	100.00
rx_break_err				1	1	100.00
	uart_intr	45.900s	0.000us	1	1	100.00
rx_timeout				1	1	100.00
	uart_intr	45.900s	0.000us	1	1	100.00
perf				1	1	100.00
	uart_perf	179.030s	0.000us	1	1	100.00
sys_loopback				1	1	100.00
	uart_loopback	9.470s	0.000us	1	1	100.00
line_loopback				1	1	100.00
	uart_loopback	9.470s	0.000us	1	1	100.00
rx_noise_filter				0	1	0.00
	uart_noise_filter	78.500s	0.000us	0	1	0.00
rx_start_bit_filter				1	1	100.00
	uart_rx_start_bit_filter	1.860s	0.000us	1	1	100.00
tx_overide				1	1	100.00
	uart_tx_ovrd	1.520s	0.000us	1	1	100.00
rx_oversample				1	1	100.00
	uart_rx_oversample	39.040s	0.000us	1	1	100.00
long_b2b_transfer				1	1	100.00
	uart_long_xfer_wo_dly	840.180s	0.000us	1	1	100.00
stress_all				1	1	100.00
	uart_stress_all	147.820s	0.000us	1	1	100.00
alert_test				1	1	100.00
	uart_alert_test	0.670s	0.000us	1	1	100.00
intr_test				1	1	100.00
	uart_intr_test	0.670s	0.000us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	uart_tl_errors	1.840s	0.000us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	uart_tl_errors	1.840s	0.000us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	uart_csr_hw_reset	0.620s	0.000us	1	1	100.00
	uart_csr_rw	0.650s	0.000us	1	1	100.00
	uart_csr_aliasing	0.580s	0.000us	1	1	100.00
	uart_same_csr_outstanding	0.740s	0.000us	1	1	100.00
tl_d_partial_access				4	4	100.00
	uart_csr_hw_reset	0.620s	0.000us	1	1	100.00
	uart_csr_rw	0.650s	0.000us	1	1	100.00
	uart_csr_aliasing	0.580s	0.000us	1	1	100.00
	uart_same_csr_outstanding	0.740s	0.000us	1	1	100.00

V2S

3/3 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	uart_tl_intg_err	1.030s	0.000us	1	1	100.00
	uart_sec_cm	1.190s	0.000us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	uart_tl_intg_err	1.030s	0.000us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	uart_stress_all_with_rand_reset	27.580s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [] vs []) check rx_empty fail: uart_rx_clk_pulses = , rx_q.size = *
	uart_noise_filter	80579085521643899883130905787383432124971350828695325121143802253980810796263	79	UVM_ERROR @ 92857545592 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 92857545592 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 92860936876 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0 UVM_ERROR @ 92860936876 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 92861110788 ps: (uart_scoreboard.sv:377) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (0 [0x0] vs 1 [0x1]) check rx_empty fail: uart_rx_clk_pulses = 0, rx_q.size = 0
UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [] vs []) check rx_idle fail: rx_en = , uart_rx_clk_pulses = *
	uart_stress_all_with_rand_reset	111466820178172611957409264970797889533539825274646909524139228925239978039232	108	UVM_ERROR @ 1818496602 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0 UVM_ERROR @ 1818496602 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1 UVM_INFO @ 1860537082 ps: (uart_tx_rx_vseq.sv:132) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_noise_filter_vseq] finished run 1/11 UVM_INFO @ 1860904426 ps: (cip_base_vseq__tl_errors.svh:292) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq] Running run_tl_errors_vseq 6/361 UVM_INFO @ 1952230515 ps: (cip_base_vseq.sv:1153) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.uart_common_vseq]