Simulation Results: adc_ctrl

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 70.25 %
  • code
  • 96.83 %
  • assert
  • 95.79 %
  • func
  • 18.14 %
  • line
  • 99.05 %
  • branch
  • 97.71 %
  • cond
  • 92.80 %
  • toggle
  • 100.00 %
  • FSM
  • 94.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.120s 5841.335us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.390s 1079.224us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.970s 379.512us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 45.830s 27075.984us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.460s 1379.403us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.660s 313.150us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.970s 379.512us 1 1 100.00
adc_ctrl_csr_aliasing 2.460s 1379.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 32.640s 329926.347us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 536.190s 315689.325us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 541.850s 332268.816us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 68.160s 165477.438us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 261.560s 587400.433us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 264.980s 593119.425us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 314.330s 202762.090us 1 1 100.00
clock_gating 1 1 100.00
adc_ctrl_clock_gating 71.480s 167735.574us 1 1 100.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 4.590s 3880.120us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 8.580s 22485.223us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 161.920s 97305.711us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 122.540s 240863.707us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.380s 487.145us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.740s 370.798us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.700s 551.113us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.700s 551.113us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.390s 1079.224us 1 1 100.00
adc_ctrl_csr_rw 0.970s 379.512us 1 1 100.00
adc_ctrl_csr_aliasing 2.460s 1379.403us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.460s 2565.878us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.390s 1079.224us 1 1 100.00
adc_ctrl_csr_rw 0.970s 379.512us 1 1 100.00
adc_ctrl_csr_aliasing 2.460s 1379.403us 1 1 100.00
adc_ctrl_same_csr_outstanding 5.460s 2565.878us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 2.970s 4548.937us 1 1 100.00
adc_ctrl_sec_cm 13.010s 7779.073us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 2.970s 4548.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 5.210s 2764.044us 1 1 100.00