Simulation Results: chip

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 73.16 %
  • code
  • 85.04 %
  • assert
  • 97.37 %
  • func
  • 37.06 %
  • line
  • 94.25 %
  • branch
  • 93.56 %
  • cond
  • 89.03 %
  • toggle
  • 91.20 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
82.37%
V2S
50.00%
V3
57.69%
unmapped
75.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 149.000s 2972.047us 1 1 100.00
chip_sw_example_rom 74.010s 2474.498us 1 1 100.00
chip_sw_example_manufacturer 175.370s 2952.804us 1 1 100.00
chip_sw_example_concurrency 144.350s 2889.558us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 168.880s 4297.302us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 328.250s 6158.252us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 275.460s 5063.937us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4572.620s 39849.195us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 268.710s 6226.267us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4572.620s 39849.195us 1 1 100.00
chip_csr_rw 328.250s 6158.252us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 6.250s 191.256us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 252.870s 3837.150us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 252.870s 3837.150us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 252.870s 3837.150us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 352.240s 4496.646us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 352.240s 4496.646us 1 1 100.00
chip_sw_uart_tx_rx_idx1 344.980s 4173.322us 1 1 100.00
chip_sw_uart_tx_rx_idx2 374.710s 4250.796us 1 1 100.00
chip_sw_uart_tx_rx_idx3 415.770s 5061.743us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 1607.830s 12742.663us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 1744.890s 13314.746us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 635.840s 8473.048us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 182.040s 4801.515us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 182.040s 4801.515us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 237.370s 3913.873us 1 1 100.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 263.940s 6534.390us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 178.600s 3358.611us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 855.080s 12678.903us 1 1 100.00
chip_tap_straps_testunlock0 134.970s 3608.515us 1 1 100.00
chip_tap_straps_rma 160.540s 3744.369us 1 1 100.00
chip_tap_straps_prod 94.660s 2811.023us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 132.160s 2825.633us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 871.300s 10132.800us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 413.490s 5314.807us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 413.490s 5314.807us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 563.070s 7770.039us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1502.000s 13595.925us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 361.650s 5018.309us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 642.100s 6194.199us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3655.300s 18930.719us 1 1 100.00
chip_sw_aes_enc_jitter_en 189.440s 3513.321us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 565.480s 6747.451us 1 1 100.00
chip_sw_hmac_enc_jitter_en 173.160s 3576.825us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1560.060s 12847.917us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 185.700s 3498.065us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 373.920s 5198.317us 1 1 100.00
chip_sw_clkmgr_jitter 186.380s 3009.540us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 215.330s 3523.963us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 369.080s 5844.847us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 263.660s 4936.156us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 217.190s 3855.247us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 263.660s 4936.156us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 173.350s 3376.634us 1 1 100.00
chip_sw_aes_smoketest 185.290s 2983.725us 1 1 100.00
chip_sw_aon_timer_smoketest 198.650s 3440.434us 1 1 100.00
chip_sw_clkmgr_smoketest 163.230s 3611.330us 1 1 100.00
chip_sw_csrng_smoketest 184.490s 3765.147us 1 1 100.00
chip_sw_entropy_src_smoketest 973.850s 8293.439us 1 1 100.00
chip_sw_gpio_smoketest 219.440s 3288.222us 1 1 100.00
chip_sw_hmac_smoketest 195.430s 3033.369us 1 1 100.00
chip_sw_kmac_smoketest 175.670s 3159.843us 1 1 100.00
chip_sw_otbn_smoketest 1372.070s 10832.963us 1 1 100.00
chip_sw_pwrmgr_smoketest 283.010s 6073.793us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 269.440s 5815.887us 1 1 100.00
chip_sw_rv_plic_smoketest 135.290s 3143.500us 1 1 100.00
chip_sw_rv_timer_smoketest 188.840s 3212.438us 1 1 100.00
chip_sw_rstmgr_smoketest 152.430s 2989.354us 1 1 100.00
chip_sw_sram_ctrl_smoketest 113.010s 2638.675us 1 1 100.00
chip_sw_uart_smoketest 175.260s 3571.611us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 164.780s 2510.898us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 334.400s 4545.420us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7848.320s 65019.014us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 2530.360s 15187.014us 1 1 100.00
chip_sw_rom_raw_unlock 1 1 100.00
rom_raw_unlock 172.160s 6725.271us 1 1 100.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 241.560s 3681.126us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 170.870s 2740.210us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7281.630s 55491.060us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7494.020s 58101.223us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 69.970s 2715.534us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 69.970s 2715.534us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4572.620s 39849.195us 1 1 100.00
chip_same_csr_outstanding 1315.790s 16357.049us 1 1 100.00
chip_csr_hw_reset 168.880s 4297.302us 1 1 100.00
chip_csr_rw 328.250s 6158.252us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4572.620s 39849.195us 1 1 100.00
chip_same_csr_outstanding 1315.790s 16357.049us 1 1 100.00
chip_csr_hw_reset 168.880s 4297.302us 1 1 100.00
chip_csr_rw 328.250s 6158.252us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 39.180s 1621.047us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 5.480s 57.750us 1 1 100.00
xbar_smoke_large_delays 55.100s 9159.265us 1 1 100.00
xbar_smoke_slow_rsp 42.090s 4253.256us 1 1 100.00
xbar_random_zero_delays 26.490s 489.287us 1 1 100.00
xbar_random_large_delays 26.110s 4031.392us 1 1 100.00
xbar_random_slow_rsp 98.000s 10923.718us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 30.430s 908.948us 1 1 100.00
xbar_error_and_unmapped_addr 20.270s 745.194us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 14.950s 306.357us 1 1 100.00
xbar_error_and_unmapped_addr 20.270s 745.194us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 11.740s 428.579us 1 1 100.00
xbar_access_same_device_slow_rsp 313.100s 35842.512us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 5.890s 78.046us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 85.240s 1497.834us 1 1 100.00
xbar_stress_all_with_error 93.000s 4093.327us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 52.180s 1092.150us 1 1 100.00
xbar_stress_all_with_reset_error 27.730s 235.120us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 2530.360s 15187.014us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 2351.050s 35091.238us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2517.980s 15517.390us 1 1 100.00
rom_e2e_boot_policy_valid 5 15 33.33
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 2093.230s 12026.584us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 2700.140s 16289.539us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 2766.280s 17045.335us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 2689.500s 16725.001us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 2476.790s 15527.475us 1 1 100.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 18.150s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 17.000s 10.380us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 16.520s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 22.230s 10.120us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 16.830s 10.280us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 17.340s 10.140us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 17.340s 10.360us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 16.480s 10.260us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 17.970s 10.280us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 17.170s 10.280us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 16.580s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 16.400s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 16.690s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 19.590s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 18.200s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 16.940s 10.260us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 20.800s 10.140us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18.880s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 21.140s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 18.460s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.900s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 16.530s 10.280us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 16.560s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 17.120s 10.160us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 16.430s 10.300us 0 1 0.00
rom_e2e_asm_init 5 5 100.00
rom_e2e_asm_init_test_unlocked0 1966.210s 12092.722us 1 1 100.00
rom_e2e_asm_init_dev 2466.340s 16482.987us 1 1 100.00
rom_e2e_asm_init_prod 2495.390s 15714.484us 1 1 100.00
rom_e2e_asm_init_prod_end 2556.080s 18634.400us 1 1 100.00
rom_e2e_asm_init_rma 2409.870s 15003.225us 1 1 100.00
rom_e2e_keymgr_init 2 3 66.67
rom_e2e_keymgr_init_rom_ext_meas 4422.430s 28527.456us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 2441.190s 15615.027us 0 1 0.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 4210.940s 29034.008us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 2634.340s 16171.740us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2958.690s 35317.613us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2958.690s 35317.613us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 171.010s 3139.702us 1 1 100.00
chip_sw_aes_enc_jitter_en 189.440s 3513.321us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 153.020s 3405.257us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 160.280s 2819.380us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1714.060s 13004.646us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 148.730s 3290.029us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 388.450s 6398.068us 1 1 100.00
chip_sw_all_escalation_resets 0 1 0.00
chip_sw_all_escalation_resets 164.770s 2770.748us 0 1 0.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 575.860s 6484.781us 1 1 100.00
chip_plic_all_irqs_10 227.720s 4023.027us 1 1 100.00
chip_plic_all_irqs_20 366.090s 4316.874us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 161.450s 3209.966us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 910.250s 10272.822us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 287.320s 5330.518us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 165.320s 2876.935us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1182.800s 8956.870us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 761.020s 6453.184us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 738.980s 8194.928us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7838.490s 255169.037us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 240.490s 3843.614us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 283.010s 6073.793us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 240.490s 3843.614us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 507.150s 7554.074us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 507.150s 7554.074us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 280.800s 7368.262us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 378.560s 5918.929us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 568.910s 5837.520us 1 1 100.00
chip_sw_aes_idle 160.280s 2819.380us 1 1 100.00
chip_sw_hmac_enc_idle 193.140s 2938.910us 1 1 100.00
chip_sw_kmac_idle 173.080s 2902.787us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 349.440s 5332.389us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 302.130s 4853.428us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 225.980s 4643.378us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 296.420s 5367.214us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 828.290s 10053.490us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 369.180s 4005.524us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 409.960s 5286.490us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 360.820s 4073.419us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 367.920s 4500.056us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 399.860s 4637.120us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 350.420s 5099.604us 1 1 100.00
chip_sw_ast_clk_outputs 563.070s 7770.039us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 670.900s 14153.765us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 360.820s 4073.419us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 367.920s 4500.056us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 361.650s 5018.309us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 642.100s 6194.199us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3655.300s 18930.719us 1 1 100.00
chip_sw_aes_enc_jitter_en 189.440s 3513.321us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 565.480s 6747.451us 1 1 100.00
chip_sw_hmac_enc_jitter_en 173.160s 3576.825us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1560.060s 12847.917us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 185.700s 3498.065us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 373.920s 5198.317us 1 1 100.00
chip_sw_clkmgr_jitter 186.380s 3009.540us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 134.220s 2405.274us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 362.100s 5503.750us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 553.050s 6970.597us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 3293.010s 25343.930us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 151.180s 2710.342us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 178.430s 3588.071us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 708.370s 8033.633us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 167.530s 3696.793us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 369.560s 5684.065us 1 1 100.00
chip_sw_flash_init_reduced_freq 1045.540s 19859.488us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 2091.940s 19452.917us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 563.070s 7770.039us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 385.850s 4313.984us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 267.200s 3421.038us 1 1 100.00
chip_sw_clkmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 164.770s 2770.748us 0 1 0.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 1182.800s 8956.870us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 790.250s 6274.756us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 0 1 0.00
chip_sw_csrng_fuse_en_sw_app_read_test 173.410s 2779.600us 0 1 0.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 472.290s 6753.521us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 162.050s 2752.295us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 3134.010s 19955.819us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 124.230s 3358.345us 1 1 100.00
chip_sw_edn_entropy_reqs 607.230s 6402.082us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 124.230s 3358.345us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 790.250s 6274.756us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 129.200s 2549.913us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1246.940s 18056.940us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 633.410s 5707.492us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 642.100s 6194.199us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 343.810s 4114.138us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 361.650s 5018.309us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3367.170s 43010.546us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1246.940s 18056.940us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 218.330s 3198.122us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1037.490s 9235.703us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.430s 2769.971us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3367.170s 43010.546us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.430s 2769.971us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.430s 2769.971us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.430s 2769.971us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.430s 2769.971us 0 1 0.00
chip_sw_flash_lc_escalate_en 0 1 0.00
chip_sw_all_escalation_resets 164.770s 2770.748us 0 1 0.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 273.130s 11726.841us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 583.870s 5542.996us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 437.430s 5596.626us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 437.430s 5596.626us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 129.770s 2550.147us 1 1 100.00
chip_sw_hmac_enc_jitter_en 173.160s 3576.825us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 193.140s 2938.910us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1626.890s 10781.682us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 729.640s 5522.700us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 398.110s 4714.105us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 404.630s 5544.917us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 365.310s 4960.614us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 267.880s 3642.961us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1037.490s 9235.703us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 1560.060s 12847.917us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 1359.130s 10412.544us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1714.060s 13004.646us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2649.410s 14935.485us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 167.390s 3315.715us 1 1 100.00
chip_sw_kmac_mode_kmac 204.770s 2534.114us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 185.700s 3498.065us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1037.490s 9235.703us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 399.160s 7523.793us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 185.230s 3670.704us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 1293.330s 9453.584us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 173.080s 2902.787us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 388.450s 6398.068us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 855.080s 12678.903us 1 1 100.00
chip_tap_straps_rma 160.540s 3744.369us 1 1 100.00
chip_tap_straps_prod 94.660s 2811.023us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 194.090s 3058.216us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 399.160s 7523.793us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 399.160s 7523.793us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 399.160s 7523.793us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 1365.940s 11411.607us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_prim_tl_access 273.130s 11726.841us 1 1 100.00
chip_rv_dm_lc_disabled 84.000s 3231.965us 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 149.430s 2769.971us 0 1 0.00
chip_sw_flash_rma_unlocked 3367.170s 43010.546us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 234.280s 3396.630us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 517.190s 7618.320us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 444.500s 5299.226us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 487.960s 6327.213us 0 1 0.00
chip_sw_lc_ctrl_transition 399.160s 7523.793us 1 1 100.00
chip_sw_keymgr_key_derivation 1037.490s 9235.703us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 358.730s 9944.583us 1 1 100.00
chip_sw_sram_ctrl_execution_main 549.570s 9707.739us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 670.900s 14153.765us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 369.180s 4005.524us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 409.960s 5286.490us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 360.820s 4073.419us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 367.920s 4500.056us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 399.860s 4637.120us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 350.420s 5099.604us 1 1 100.00
chip_tap_straps_dev 855.080s 12678.903us 1 1 100.00
chip_tap_straps_rma 160.540s 3744.369us 1 1 100.00
chip_tap_straps_prod 94.660s 2811.023us 1 1 100.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 192.140s 3546.123us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 92.250s 3210.389us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 79.470s 3242.477us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 102.120s 3092.779us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_rv_dm_lc_disabled 84.000s 3231.965us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1418.410s 23283.256us 1 1 100.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 662.840s 11664.273us 0 1 0.00
chip_sw_lc_walkthrough_prod 775.470s 9640.268us 0 1 0.00
chip_sw_lc_walkthrough_prodend 691.610s 9285.039us 1 1 100.00
chip_sw_lc_walkthrough_rma 414.160s 7020.535us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1418.410s 23283.256us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 3 3 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 64.400s 2518.784us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 65.240s 2198.975us 1 1 100.00
rom_volatile_raw_unlock 59.330s 2243.925us 1 1 100.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3424.740s 17419.307us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3655.300s 18930.719us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 568.910s 5837.520us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 568.910s 5837.520us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 568.910s 5837.520us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 294.940s 3280.964us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 399.160s 7523.793us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1246.940s 18056.940us 1 1 100.00
chip_sw_otbn_mem_scramble 294.940s 3280.964us 1 1 100.00
chip_sw_keymgr_key_derivation 1037.490s 9235.703us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 324.730s 4398.087us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 142.170s 2878.969us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1246.940s 18056.940us 1 1 100.00
chip_sw_otbn_mem_scramble 294.940s 3280.964us 1 1 100.00
chip_sw_keymgr_key_derivation 1037.490s 9235.703us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 324.730s 4398.087us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 142.170s 2878.969us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 399.160s 7523.793us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 348.890s 4110.516us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 194.090s 3058.216us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_prim_tl_access 273.130s 11726.841us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 234.280s 3396.630us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 517.190s 7618.320us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 444.500s 5299.226us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 487.960s 6327.213us 0 1 0.00
chip_sw_lc_ctrl_transition 399.160s 7523.793us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 273.130s 11726.841us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 865.000s 7214.299us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 274.820s 7101.600us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1278.440s 25477.685us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 232.610s 7677.311us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 350.070s 7767.771us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 451.990s 6916.299us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 756.870s 23632.687us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 2 2 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1056.120s 15082.408us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 507.150s 7554.074us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 921.680s 14474.226us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 392.780s 5157.229us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 274.820s 7101.600us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 309.080s 4375.925us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1053.410s 17032.780us 0 1 0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 284.940s 7149.063us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 296.720s 7208.435us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 614.710s 15028.666us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 628.990s 7906.197us 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1006.320s 11568.460us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1795.070s 24860.281us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 180.030s 3061.167us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 164.770s 2770.748us 0 1 0.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 358.730s 9944.583us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 358.730s 9944.583us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 1006.320s 11568.460us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 614.710s 15028.666us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 392.780s 5157.229us 1 1 100.00
chip_sw_pwrmgr_smoketest 283.010s 6073.793us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 341.280s 4785.682us 1 1 100.00
chip_sw_rstmgr_cpu_info 0 1 0.00
chip_sw_rstmgr_cpu_info 236.830s 3648.869us 0 1 0.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 262.310s 4115.111us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 910.250s 10272.822us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 157.890s 3468.144us 1 1 100.00
chip_sw_rstmgr_escalation_reset 0 1 0.00
chip_sw_all_escalation_resets 164.770s 2770.748us 0 1 0.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 761.020s 6453.184us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 433.690s 4601.627us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 492.730s 5147.715us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 174.270s 3039.422us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 142.170s 2878.969us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 0 1 0.00
chip_sw_rstmgr_cpu_info 236.830s 3648.869us 0 1 0.00
chip_sw_rv_core_ibex_double_fault 0 1 0.00
chip_sw_rstmgr_cpu_info 236.830s 3648.869us 0 1 0.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 719.690s 10443.460us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 839.990s 14105.256us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 341.280s 4785.682us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 221.390s 3895.116us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 296.270s 5787.481us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 160.540s 3744.369us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 84.000s 3231.965us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 575.860s 6484.781us 1 1 100.00
chip_plic_all_irqs_10 227.720s 4023.027us 1 1 100.00
chip_plic_all_irqs_20 366.090s 4316.874us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 120.680s 2385.607us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 162.040s 3189.155us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 2530.360s 15187.014us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 414.030s 6754.204us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 182.500s 3112.304us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 233.170s 3264.585us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 165.540s 3397.748us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 324.730s 4398.087us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 373.920s 5198.317us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 448.710s 7972.427us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 476.030s 8144.042us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 549.570s 9707.739us 1 1 100.00
chip_sw_sram_lc_escalation 1 2 50.00
chip_sw_all_escalation_resets 164.770s 2770.748us 0 1 0.00
chip_sw_data_integrity_escalation 413.490s 5314.807us 1 1 100.00
chip_sw_sysrst_ctrl_reset 2 2 100.00
chip_sw_pwrmgr_sysrst_ctrl_reset 628.990s 7906.197us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1082.720s 24490.911us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 136.440s 2377.080us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 234.720s 3762.115us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 319.390s 4350.575us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 1082.720s 24490.911us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 1082.720s 24490.911us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2399.290s 20777.939us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2399.290s 20777.939us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 325.090s 6178.840us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2958.690s 35317.613us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 153.810s 2895.789us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 177.480s 2972.472us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 248.210s 3594.651us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 298.670s 3506.237us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 1035.300s 7847.895us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5069.270s 31693.191us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1774.430s 12418.185us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 130.890s 3114.799us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 211.140s 2672.850us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 111.350s 2740.819us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 8953.720s 71807.770us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1043.490s 6982.990us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 176.120s 3734.419us 0 1 0.00
rom_e2e_jtag_debug_dev 375.880s 6827.142us 0 1 0.00
rom_e2e_jtag_debug_rma 540.490s 15063.751us 0 1 0.00
rom_e2e_jtag_inject 0 3 0.00
rom_e2e_jtag_inject_test_unlocked0 53.410s 2347.605us 0 1 0.00
rom_e2e_jtag_inject_dev 68.540s 3354.186us 0 1 0.00
rom_e2e_jtag_inject_rma 53.530s 2382.610us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 11.190s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 267.230s 3577.131us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 276.950s 3077.913us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 930.830s 6089.063us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 796.230s 6839.026us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 241.630s 2196.442us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 641.830s 6041.790us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 57.700s 2332.159us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 204.040s 3015.092us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 0 1 0.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 316.850s 6920.459us 0 1 0.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 306.570s 4931.284us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 1006.320s 11568.460us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 176.120s 3734.419us 0 1 0.00
rom_e2e_jtag_debug_dev 375.880s 6827.142us 0 1 0.00
rom_e2e_jtag_debug_rma 540.490s 15063.751us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 309.680s 5288.831us 1 1 100.00
chip_sw_plic_alerts 0 1 0.00
chip_sw_all_escalation_resets 164.770s 2770.748us 0 1 0.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5447.630s 38138.969us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5447.630s 38138.969us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 170.450s 3428.523us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 352.240s 4496.646us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3106.290s 19476.880us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 6 8 75.00
chip_sival_flash_info_access 192.950s 3490.959us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 452.270s 5924.958us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 5.090s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 123.740s 2187.743us 1 1 100.00
chip_sw_otp_ctrl_descrambling 191.240s 3276.443us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 193.830s 4161.633us 1 1 100.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.679s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 182.310s 3129.791us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 18761829092779520097293474025171832738946708070579445967376686587251741106116 217
UVM_ERROR @ 2715.534330 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 1, but saw 0).
TL item was: req: (cip_tl_seq_item@41159) { a_addr: 'h104a8 a_data: 'h199326b2 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h20 a_opcode: 'h4 a_user: 'h1a91a d_param: 'h0 d_source: 'h20 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2715.534330 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_rstmgr_cpu_info 53316273797844830503702303934585995617071959378015446346391960295063457604246 333
UVM_ERROR @ 3648.869186 us: (cip_base_scoreboard.sv:575) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted 0, but saw 1).
TL item was: req: (cip_tl_seq_item@98251) { a_addr: 'h8 a_data: 'h0 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h0 a_opcode: 'h0 a_user: 'h259aa d_param: 'h0 d_source: 'h0 d_data: 'h0 d_size: 'h2 d_opcode: 'h0 d_error: 'h1 d_sink: 'h0 d_user: 'h1f2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{}.
UVM_INFO @ 3648.869186 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 42034297764983423487097599774187040507005650619459300776859838086824125208620 225
UVM_ERROR @ 3231.965256 us: (cip_base_vseq.sv:649) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10638 read out mismatch
UVM_INFO @ 3231.965256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected *, got *
chip_sw_all_escalation_resets 15439832137905465060502477683255309641118287887501596270548801217891685184469 317
UVM_ERROR @ 2770.747788 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:635)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
UVM_INFO @ 2770.747788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 10735773646407244044983194030209795273041118884082583171929353922199882264607 322
UVM_ERROR @ 3112.304239 us: (chip_sw_spi_passthrough_collision_vseq.sv:183) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_spi_passthrough_collision_vseq] Compare mismatch
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 60001023863192971028885611207839558263121933464394867930146416330573363364351 309
UVM_ERROR @ 2769.971210 us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 35 is asserted but not expected
UVM_INFO @ 2769.971210 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 76778001165553988306130270478907749316448643849858408459053946171028331669591 342
UVM_ERROR @ 6327.212856 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
UVM_INFO @ 6327.212856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 54913379792630420833507196317707260220074805318761985812110881209562658645950 316
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 3015.091856 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3015.091856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_csrng_fuse_en_sw_app_read_test 49423865670235618927356159759485096458385537166898686217902782837242214313909 312
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
UVM_ERROR @ 2779.599820 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 2779.599820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 14537372272963598972581067114992011365719991814331847068234533649401850608328 282
UVM_FATAL @ 0.000000 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.24.vmem could not be opened for r mode
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 112434631586057674213450144749156465735611938649452866320647440620025243369466 369
UVM_ERROR @ 11664.273000 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 11664.273000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 50700682103741973862773565390322029580507800153974247802968043920310427540438 369
UVM_ERROR @ 9640.267960 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 9640.267960 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 73447131088152808881906899834798056105555141941645052310686359625684749951126 341
UVM_ERROR @ 7020.535386 us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 47 is asserted but not expected
UVM_INFO @ 7020.535386 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 76621497963541296855641069509005787961243968765603308582523897359581993116614 344
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 15028.666000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 15028.666000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 40480060912109044677319382793246157090887544372488353087036546488537600510471 325
Offending '(rstreqs[0] && (reset_cause == HwReq))'
UVM_ERROR @ 7767.771000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7767.771000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_random_sleep_power_glitch_reset 75079124938805576108917740743639773542796249240726702333080125986048161707190 364
Offending '(rstreqs[1] && (reset_cause == HwReq))'
UVM_ERROR @ 17032.779500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 17032.779500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 96471726792896261824998310291560255348969797419474626866230604097278821793913 332
UVM_ERROR @ 35317.612731 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns
UVM_INFO @ 35317.612731 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!
chip_sw_alert_test 101878525480636015100913338263057454336287479343134671053489025429186469147290 307
UVM_ERROR @ 3290.029167 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert 52!
UVM_INFO @ 3290.029167 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 114295968855697625533925692495934236319197371192235474454860917748033257662316 308
UVM_ERROR @ 2876.935020 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
UVM_INFO @ 2876.935020 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes
chip_sw_alert_handler_lpg_sleep_mode_pings 66336993449769179119801731888159029084791259663709283498227787223086282263623 None
Job timed out after 240 minutes
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 23030378887292077903013217019123967242762813858071019344080733035307174493329 343
UVM_ERROR @ 3577.130779 us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert 25 is asserted but not expected
UVM_INFO @ 3577.130779 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned non-zero exit code
chip_sw_pwrmgr_sleep_wake_5_bug 45281559061401599414785800420152274363526209389768576101949463472069410327978 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 110919778732993356948847007420953207177177128450751169421147926430608358477025 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:* = ErrorError
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 16239964565339585984294568950857685461814328995143039797797807918383747947741 317
UVM_ERROR @ 6920.458776 us: (sw_logger_if.sv:526) [pwrmgr_sensor_ctrl_deep_sleep_wake_up_sim_dv(sw/device/tests/pwrmgr_sensor_ctrl_deep_sleep_wake_up.c:120)] CHECK-STATUS-fail: @@@:0 = ErrorError
UVM_INFO @ 6920.458776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 68120596728616553834797041035620978227246198687142874190614330948089511743586 327
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 115142108161061804291610614852306616152908268450749307919208138840078605171288 319
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 43718915713613337072586653950151515607465145023416422585485791129596807279261 352
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_test_unlocked0 38003710864490858454673981431253720580985711296195791713122487116908823125724 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 24903585524874716170627870745887537170594620164765323559398710663750892306322 305
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 89663024382950827627967848193330840108016833843984534868017256756909310371094 303
Error-[NOA] Null object access
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [*] vs * [*]) Major alert did not match expectation.
chip_sw_rv_core_ibex_lockstep_glitch 60694522542868448559219968332782429908236937412053816440406996423048162942951 327
UVM_FATAL @ 2740.818608 us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [uvm_test_top.env.virtual_sequencer.chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (0 [0x0] vs 1 [0x1]) Major alert did not match expectation.
UVM_INFO @ 2740.818608 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 6275845665570607488510449310888766799301267327801369635689999051488456841165 312
UVM_ERROR @ 3681.126000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 3681.126000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 71843407868835052098535372762568874006537333401574544666678235161150765217928 318
UVM_ERROR @ 2740.210000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong. rcv : 2 exp : 32
UVM_INFO @ 2740.210000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 91301400260816339948585803022111712310208420034846752881637602023596768820608 327
UVM_ERROR @ 13595.924660 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ 4294967271 expected to fire. Actual IRQ state = 1
UVM_INFO @ 13595.924660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 96946706409924253613102984272724282424794879490860072223084773188841750457436 351
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_dev 44529738356472625333033050460154149870910068336300223551588666379291597895825 348
UVM_FATAL @ 10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod 42458174197501944294647188223642971254612465499140832208896128009720059372006 350
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 21375416252863294964082738768947217989182289014560233729385463047875901738845 348
UVM_FATAL @ 10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_good_b_bad_rma 9984131698279423471467390793576996589332901711143075007862478655598389094130 348
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 111081994442170110532217713269920630226149086961108896507342290435779761679502 346
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_dev 109704272971933840696916754307788397086563816749491471601544525155629878753139 349
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod 26088418585500884380574278080815861267012517938049435664495881254646953995876 349
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 107437297695040735039566726777551904554071826124126954850830586531588931914796 347
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_boot_policy_valid_a_bad_b_good_rma 62083153209106662481249588351735389156006345428057987674396388626697563082659 347
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod 96234094111492723301369890183938714881545539610463342116390935847182667235766 360
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 11332886906330742948154591023363843266232882544381854339380495055488482925071 360
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 99755356259652388005289829281594050189352109101936108699497001786700397286074 358
UVM_FATAL @ 10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18132038966752801095566365134131892858316401445400515171906080657528236260790 323
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 43060156686272069772320946127447795385917142085747955156419148526412268015546 323
UVM_FATAL @ 10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 79223138398114999851296180710964588407189109850671008258010906168698810832883 323
UVM_FATAL @ 10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 21368049954205080604122298194521945606251520344561241233689899276148536263694 357
UVM_FATAL @ 10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 88813868032572071386921296948396524265782032037152384100210523470974255617974 323
UVM_FATAL @ 10.260001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 11827130417598155213547735817241499509736733317068235817786538020750767979544 361
UVM_FATAL @ 10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 55564754749456391702345148108050208311868488534761831730560441126206186071921 323
UVM_FATAL @ 10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 84708850757106749993595953242424468577738854321106526367355891816382978864479 323
UVM_FATAL @ 10.220001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 11895883238282793191280381866669447296649957656226657825772099983627610940741 325
UVM_FATAL @ 10.280001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 18263948385582902906925345383346508204783891412510152796618033733276124528810 325
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 36276971059560708743142257651641569634209981416555546328393862747872612155533 325
UVM_FATAL @ 10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 35994092870699945961689999925157159600816400906581931876380945040652648697750 324
UVM_FATAL @ 10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
rom_e2e_jtag_debug_rma 53982031499248773730177323464114473087264831379131638081297614186569301374583 330
UVM_FATAL @ 15063.751288 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
UVM_INFO @ 15063.751288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
rom_e2e_keymgr_init_rom_ext_no_meas 56887853503339141387742387110422546766343339759748912549247072352161284483898 319
UVM_ERROR @ 15615.027125 us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_no_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns 13
UVM_INFO @ 15615.027125 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 78752272917914418183032786635484335703149081628875597398762314917588265210955 327
Offending '$stable(key_data_i)'
UVM_ERROR @ 4545.420418 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4545.420418 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---