Simulation Results: clkmgr

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.93 %
  • code
  • 98.23 %
  • assert
  • 95.48 %
  • func
  • 85.08 %
  • line
  • 98.97 %
  • branch
  • 98.57 %
  • cond
  • 94.44 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.790s 55.536us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.730s 18.080us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.690s 15.569us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.000s 261.599us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.880s 20.593us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.380s 34.430us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.690s 15.569us 1 1 100.00
clkmgr_csr_aliasing 0.880s 20.593us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.710s 32.343us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.980s 122.250us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.640s 19.124us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.670s 15.926us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.790s 55.536us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 5.830s 1280.343us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 3.700s 1364.092us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 5.830s 1280.343us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 3.000s 970.675us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.650s 17.701us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.160s 229.663us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.160s 229.663us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 18.080us 1 1 100.00
clkmgr_csr_rw 0.690s 15.569us 1 1 100.00
clkmgr_csr_aliasing 0.880s 20.593us 1 1 100.00
clkmgr_same_csr_outstanding 1.130s 50.653us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.730s 18.080us 1 1 100.00
clkmgr_csr_rw 0.690s 15.569us 1 1 100.00
clkmgr_csr_aliasing 0.880s 20.593us 1 1 100.00
clkmgr_same_csr_outstanding 1.130s 50.653us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.790s 18.998us 0 1 0.00
clkmgr_tl_intg_err 1.940s 168.330us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.960s 490.799us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.960s 490.799us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.960s 490.799us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.960s 490.799us 1 1 100.00
shadow_reg_update_error_with_csr_rw 0 1 0.00
clkmgr_shadow_reg_errors_with_csr_rw 2.450s 447.918us 0 1 0.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.940s 168.330us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 5.830s 1280.343us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 3.700s 1364.092us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.960s 490.799us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.910s 89.607us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.870s 103.263us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.740s 59.874us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.700s 42.110us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.850s 110.492us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.690s 15.569us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.790s 18.998us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.690s 15.569us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.690s 15.569us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.790s 18.998us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.570s 1464.911us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 18.230s 4726.094us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 56956950582587129542943565400010244598421514518450846515523392622881116497691 83
UVM_ERROR @ 18998422 ps: (cip_base_vseq.sv:1022) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] expect alert:fatal_fault to fire
UVM_INFO @ 18998422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_common_vseq.sv:50) [clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_fault does not trigger!
clkmgr_shadow_reg_errors_with_csr_rw 83833779625627125625053590203374913070881878250948308662613889707053237557038 76
UVM_ERROR @ 447918279 ps: (clkmgr_common_vseq.sv:50) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == 1 (0 [0x0] vs 1 [0x1]) fatal error fatal_fault does not trigger!
UVM_INFO @ 447918279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---