Simulation Results: edn/edn0

 
30/03/2026 17:32:01 DVSim: v1.17.3 sha: 554040f json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.28 %
  • code
  • 80.87 %
  • assert
  • 95.01 %
  • func
  • 79.96 %
  • line
  • 97.28 %
  • branch
  • 90.52 %
  • cond
  • 84.79 %
  • toggle
  • 82.32 %
  • FSM
  • 49.46 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.050s 24.915us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.860s 24.536us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.800s 44.910us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.320s 239.370us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.230s 88.681us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.950s 36.405us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.800s 44.910us 1 1 100.00
edn_csr_aliasing 1.230s 88.681us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.960s 36.743us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.960s 36.743us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.960s 36.743us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.010s 22.779us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.000s 23.357us 1 1 100.00
errs 1 1 100.00
edn_err 1.080s 25.605us 1 1 100.00
disable 2 2 100.00
edn_disable 0.800s 33.196us 1 1 100.00
edn_disable_auto_req_mode 1.080s 76.892us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.840s 476.894us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.920s 158.529us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.770s 33.738us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.740s 40.525us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.740s 40.525us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.860s 24.536us 1 1 100.00
edn_csr_rw 0.800s 44.910us 1 1 100.00
edn_csr_aliasing 1.230s 88.681us 1 1 100.00
edn_same_csr_outstanding 0.830s 28.143us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.860s 24.536us 1 1 100.00
edn_csr_rw 0.800s 44.910us 1 1 100.00
edn_csr_aliasing 1.230s 88.681us 1 1 100.00
edn_same_csr_outstanding 0.830s 28.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.560s 72.788us 1 1 100.00
edn_sec_cm 4.030s 645.349us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.910s 52.144us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.000s 23.357us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.030s 645.349us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.030s 645.349us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.030s 645.349us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.030s 645.349us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.000s 23.357us 1 1 100.00
edn_sec_cm 4.030s 645.349us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.000s 23.357us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.560s 72.788us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 30.000s 4469.642us 1 1 100.00